From patchwork Wed Sep 27 21:03:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nirmoy Das X-Patchwork-Id: 13401682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20CC6E82CDB for ; Wed, 27 Sep 2023 21:11:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA54D10E0C5; Wed, 27 Sep 2023 21:11:11 +0000 (UTC) X-Greylist: delayed 423 seconds by postgrey-1.36 at gabe; Wed, 27 Sep 2023 21:11:10 UTC Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 34D1D10E0C5; Wed, 27 Sep 2023 21:11:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695849070; x=1727385070; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4AwzCmdIVsBShkNTVJTgG/O9iQ0HAbqAsMHzTJRLx5U=; b=LGEql6t37ZkyO354KX/yDgLjW0SgloiKQL5QlzFBd9xZy7CA9+DIk9eM uoKHdoCveJDCyWEgG0TmGMq3/Ks7UCwP8yyaT2vQvOZOReM7q8byolNT4 D92ySJz9U6YAtmKpbqKXcLt+heWtFUlJJq6JdpiSfMdDgouFqZUdqv23p riTK3jn4PyQUtx7YVQcPF9RzLIWhvVZaRtKTgi0DK+Ah60h6efSi6L4C5 JcJWRaYDwv0FRISiaV4amAf0fPFoaylc8GgJeOBfLPu0Um/4hKhNAi8eF cxFZ3vVKwp7T3Jha5A+Rn93FiffeJHjtG36lyIPc2Liho5aY304l03oWP Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="3470802" X-IronPort-AV: E=Sophos;i="6.03,182,1694761200"; d="scan'208";a="3470802" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2023 14:04:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="864987665" X-IronPort-AV: E=Sophos;i="6.03,182,1694761200"; d="scan'208";a="864987665" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2023 14:04:05 -0700 From: Nirmoy Das To: intel-gfx@lists.freedesktop.org Date: Wed, 27 Sep 2023 23:03:54 +0200 Message-ID: <20230927210357.17461-1-nirmoy.das@intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 Subject: [Intel-gfx] [PATCH v6 1/4] drm/i915: Introduce intel_gt_mcr_lock_reset() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, dri-devel@lists.freedesktop.org, Nirmoy Das Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Implement intel_gt_mcr_lock_reset() to provide a mechanism for resetting the steer semaphore when absolutely necessary. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 29 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 1 + 2 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index bf4a933de03a..d98e0d2fc2ee 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -419,6 +419,35 @@ void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags) intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); } +/** + * intel_gt_mcr_lock_reset - Reset MCR steering lock + * @gt: GT structure + * + * Performs a steer semaphore reset operation. On MTL and beyond, a hardware + * lock will also be taken to serialize access not only for the driver, + * but also for external hardware and firmware agents. + * However, there may be situations where the driver must reset the semaphore + * but only when it is absolutely certain that no other agent should own the + * lock at that given time. + * + * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this + * function is called, although it may be acquired after this + * function call. + */ +void intel_gt_mcr_lock_reset(struct intel_gt *gt) +{ + unsigned long __flags; + + lockdep_assert_not_held(>->uncore->lock); + + spin_lock_irqsave(>->mcr_lock, __flags); + + if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) + intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); + + spin_unlock_irqrestore(>->mcr_lock, __flags); +} + /** * intel_gt_mcr_read - read a specific instance of an MCR register * @gt: GT structure diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h index 41684495b7da..485c7711f2e8 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h @@ -11,6 +11,7 @@ void intel_gt_mcr_init(struct intel_gt *gt); void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags); void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags); +void intel_gt_mcr_lock_reset(struct intel_gt *gt); u32 intel_gt_mcr_read(struct intel_gt *gt, i915_mcr_reg_t reg,