From patchwork Fri Oct 6 18:20:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 13411829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D392E92FE0 for ; Fri, 6 Oct 2023 18:31:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ABDD810E55A; Fri, 6 Oct 2023 18:31:39 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6FDEC10E556 for ; Fri, 6 Oct 2023 18:31:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696617095; x=1728153095; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bcSX2+D4e1bIr9aUxgrNrhX9AG1NKFMR0HjEUurwKOE=; b=g72b5GAKLWVX1zXIAcms2L5LIzO01II1JeC4qwTPgbAzFvCj4ZM1MtJg Iddt7UROqMKATRaqrblnwl6QzzqqbmhK4EgLG/Eqt24ctKO7Q+fdWlG5/ RmQ6sNNg0GABQvpxTxBUmCT0Tpn24aDNyiS1wswQqcZO0JZxXa2NEbI/3 lb3SQWutaKDx6pPpWSNGlrxrZqfDt8UWuJXSobMJCV3/r0eK9XijX8y1Z ERM6PG1LXKKD6XC4FFCGcv0aCmUopxgvJlUPw2NPLimf8njlJ8rPp5EDd pV5nR58i9lOhcSsywxGFFhyyJlVpdXCCCRNcQRX2ZQ9sU2Mfsu11rWAGV A==; X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="387688169" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="387688169" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 11:31:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10855"; a="745950588" X-IronPort-AV: E=Sophos;i="6.03,204,1694761200"; d="scan'208";a="745950588" Received: from dut-internal-9dd7.jf.intel.com ([10.165.21.194]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 11:31:34 -0700 From: Jonathan Cavitt To: intel-gfx@lists.freedesktop.org Date: Fri, 6 Oct 2023 11:20:49 -0700 Message-Id: <20231006182051.1599923-6-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231006182051.1599923-1-jonathan.cavitt@intel.com> References: <20231006182051.1599923-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 5/7] drm/i915: No TLB invalidation on wedged GT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com, matthew.d.roper@intel.com, jonathan.cavitt@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It is not an error for GuC TLB invalidations to fail when the GT is wedged or disabled, so do not process a wait failure as one in guc_send_invalidate_tlb. Signed-off-by: Fei Yang Signed-off-by: Jonathan Cavitt CC: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 4ed6e9e759007..ddb3115715e41 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -32,6 +32,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "i915_irq.h" #include "i915_trace.h" /** @@ -4759,6 +4760,14 @@ static long must_wait_woken(struct wait_queue_entry *wq_entry, long timeout) return timeout; } +static bool intel_gt_is_enabled(const struct intel_gt *gt) +{ + /* Check if GT is wedged or suspended */ + if (intel_gt_is_wedged(gt) || !intel_irqs_enabled(gt->i915)) + return false; + return true; +} + static int guc_send_invalidate_tlb(struct intel_guc *guc, enum intel_guc_tlb_inval_mode type) { struct intel_guc_tlb_wait _wq, *wq = &_wq; @@ -4810,7 +4819,8 @@ static int guc_send_invalidate_tlb(struct intel_guc *guc, enum intel_guc_tlb_inv if (err) goto out; - if (!must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) { + if (intel_gt_is_enabled(guc_to_gt(guc)) && + !must_wait_woken(&wait, intel_guc_ct_expected_delay(&guc->ct))) { guc_err(guc, "TLB invalidation response timed out for seqno %u\n", seqno); err = -ETIME;