From patchwork Mon Oct 9 17:29:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 13414163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FABDCD6117 for ; Mon, 9 Oct 2023 17:40:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7450C10E29B; Mon, 9 Oct 2023 17:40:08 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C76B510E0BA for ; Mon, 9 Oct 2023 17:40:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696873202; x=1728409202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vm8DfDBOzQxRSTvug5xvF6Vi+KptExX1yPmE9Kfqadk=; b=THM8eOQ6nqaXRnMtGshx/Mdy5AaId9qJRnnVj9BHBKohEurEVCnW6twW zGxTF7jU8+67kQp8XRh6Os/NtTOJZZIE8bpycv0R/JRvJxT5Y+RUThD6k xWXt68yoQDRlBzuhI9whuL+qV5eRJhPx2ViFo2z37uvFKL77ArRZ4DB6q V6GUwfSlM2GzngBD40zTvni8pkKDcuIWbdoOa12sgYVc5IFulJ90env59 02PsYZpkTcdfKIlhi6Fj1EzHf4hyWgn8L8roUui5vYWJ1ZiXZZ49yN8kU gZ/gpze2H6URnaAI2pgecSWnj+iy1Nk/cbEH+RP3ZJQz+xBqxXv2HANHF Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="450705021" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="450705021" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 10:40:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="788251454" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="788251454" Received: from dut-internal-9dd7.jf.intel.com ([10.165.21.194]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 10:40:01 -0700 From: Jonathan Cavitt To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2023 10:29:18 -0700 Message-Id: <20231009172919.1769055-7-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231009172919.1769055-1-jonathan.cavitt@intel.com> References: <20231009172919.1769055-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com, matthew.d.roper@intel.com, jonathan.cavitt@intel.com, saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com, nirmoy.das@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For the gt_tlb live selftest, when operating on the GSC engine, increase the timeout from 10 ms to 200 ms because the GSC engine is a bit slower than the rest. Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c index 7e41f69fc818f..24beb94aa7a37 100644 --- a/drivers/gpu/drm/i915/gt/selftest_tlb.c +++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c @@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce, i915_request_get(rq); i915_request_add(rq); - /* Short sleep to sanitycheck the batch is spinning before we begin */ - msleep(10); + /* + * Short sleep to sanitycheck the batch is spinning before we begin. + * FIXME: Why is GSC so slow? + */ + if (ce->engine->class == OTHER_CLASS) + msleep(200); + else + msleep(20); + if (va == vb) { if (!i915_request_completed(rq)) { pr_err("%s(%s): Semaphore sanitycheck failed %llx, with alignment %llx, using PTE size %x (phys %x, sg %x)\n",