diff mbox series

[23/29] drm/i915/dp_mst: Enable DSC passthrough

Message ID 20231024010925.3949910-24-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Improve BW management on MST links | expand

Commit Message

Imre Deak Oct. 24, 2023, 1:09 a.m. UTC 
Enable passing through DSC streams to the sink in last branch devices.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a7eb31b489947..bb8951f89f61f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2950,6 +2950,24 @@  intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
 			    str_enable_disable(enable));
 }
 
+static void
+intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
+				  bool enable)
+{
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct drm_dp_aux *aux = connector->port ?
+				 connector->port->passthrough_aux : NULL;
+
+	if (!aux)
+		return;
+
+	if (drm_dp_dpcd_writeb(aux, DP_DSC_PASSTHROUGH_EN,
+			       enable ? DP_DSC_PASSTHROUGH_EN : 0) < 0)
+		drm_dbg_kms(&i915->drm,
+			    "Failed to %s sink compression passthrough state\n",
+			    str_enable_disable(enable));
+}
+
 void intel_dp_sink_set_decompression_state(struct intel_connector *connector,
 					   const struct intel_crtc_state *crtc_state,
 					   bool enable)
@@ -2962,7 +2980,13 @@  void intel_dp_sink_set_decompression_state(struct intel_connector *connector,
 	if (drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux))
 		return;
 
-	intel_dp_sink_set_dsc_decompression(connector, enable);
+	if (enable) {
+		intel_dp_sink_set_dsc_passthrough(connector, true);
+		intel_dp_sink_set_dsc_decompression(connector, true);
+	} else {
+		intel_dp_sink_set_dsc_decompression(connector, false);
+		intel_dp_sink_set_dsc_passthrough(connector, false);
+	}
 }
 
 static void