| Message ID | 20231111114320.87277-2-vinod.govindapillai@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/xe2lpd: WA for underruns during FBC enable | expand |
> -----Original Message----- > From: Govindapillai, Vinod <vinod.govindapillai@intel.com> > Sent: Saturday, November 11, 2023 1:43 PM > To: intel-gfx@lists.freedesktop.org > Cc: Govindapillai, Vinod <vinod.govindapillai@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Saarinen, Jani > <jani.saarinen@intel.com>; Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>; Kahola, Mika <mika.kahola@intel.com> > Subject: [PATCH v4 1/1] drm/i915/xe2lpd: implement WA for underruns while enabling FBC > > FIFO underruns are observed when FBC is enabled on plane 2 or plane 3. Recommended WA is to update the FBC enabling > sequence. > The plane binding register bits need to be updated separately before programming the FBC enable bit. > > Bspec: 74151 > Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v3 Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index bde12fe62275..b73cf1c5ba33 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) static void ivb_fbc_activate(struct intel_fbc *fbc) { > struct drm_i915_private *i915 = fbc->i915; > + u32 dpfc_ctl; > > if (DISPLAY_VER(i915) >= 10) > glk_fbc_program_cfb_stride(fbc); > @@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) > if (intel_gt_support_legacy_fencing(to_gt(i915))) > snb_fbc_program_fence(fbc); > > + /* wa_14019417088 Alternative WA*/ > + dpfc_ctl = ivb_dpfc_ctl(fbc); > + if (DISPLAY_VER(i915) >= 20) > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); > + > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), > - DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); > + DPFC_CTL_EN | dpfc_ctl); > } > > static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) > -- > 2.34.1
On Sat, Nov 11, 2023 at 01:43:20PM +0200, Vinod Govindapillai wrote: > FIFO underruns are observed when FBC is enabled on plane 2 or > plane 3. Recommended WA is to update the FBC enabling sequence. > The plane binding register bits need to be updated separately > before programming the FBC enable bit. > > Bspec: 74151 > Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v3 > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index bde12fe62275..b73cf1c5ba33 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) > static void ivb_fbc_activate(struct intel_fbc *fbc) > { > struct drm_i915_private *i915 = fbc->i915; > + u32 dpfc_ctl; > > if (DISPLAY_VER(i915) >= 10) > glk_fbc_program_cfb_stride(fbc); > @@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) > if (intel_gt_support_legacy_fencing(to_gt(i915))) > snb_fbc_program_fence(fbc); > > + /* wa_14019417088 Alternative WA*/ > + dpfc_ctl = ivb_dpfc_ctl(fbc); > + if (DISPLAY_VER(i915) >= 20) Workarounds should never be ">=." When they first show up in the workaround database, they apply to some or all steppings of one very specific IP version and only get carried forward to additional IP versions and platforms when the workaround database also lists those additional versions under the same lineage number. In this case this workaround applies to all steppings of display IP version 20.0 so we should be matching on that exactly so that we don't apply this to future platforms where it isn't wanted. Matt > + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); > + > intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), > - DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); > + DPFC_CTL_EN | dpfc_ctl); > } > > static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index bde12fe62275..b73cf1c5ba33 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -608,6 +608,7 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) static void ivb_fbc_activate(struct intel_fbc *fbc) { struct drm_i915_private *i915 = fbc->i915; + u32 dpfc_ctl; if (DISPLAY_VER(i915) >= 10) glk_fbc_program_cfb_stride(fbc); @@ -617,8 +618,13 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (intel_gt_support_legacy_fencing(to_gt(i915))) snb_fbc_program_fence(fbc); + /* wa_14019417088 Alternative WA*/ + dpfc_ctl = ivb_dpfc_ctl(fbc); + if (DISPLAY_VER(i915) >= 20) + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), - DPFC_CTL_EN | ivb_dpfc_ctl(fbc)); + DPFC_CTL_EN | dpfc_ctl); } static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)