diff mbox series

[4/4] drm/dp_mst: Fix PBN divider calculation for UHBR rates

Message ID 20231113201110.510724-4-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm/i915/dp: Account for channel coding efficiency on UHBR links | expand

Commit Message

Imre Deak Nov. 13, 2023, 8:11 p.m. UTC
The current way of calculating the pbn_div value, the link BW per each
MTP slot, worked only for DP 1.4 link rates. Fix things up for UHBR
rates calculating with the correct channel coding efficiency based on
the link rate.

On UHBR the resulting pbn_div value is not an integer (vs. DP 1.4 where
the value is always an integer), so ideally a scaled value containing
the fractional part should be returned, so that the PBN -> MTP slot
count (aka TU size) conversion can be done with less error. For now
return a rounded-down value - which can result in +1 excess MTP slot
getting allocated on UHBR links.

Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c | 15 +++++++++++++--
 include/drm/display/drm_dp_helper.h           | 13 +++++++++++++
 2 files changed, 26 insertions(+), 2 deletions(-)

Comments

kernel test robot Nov. 13, 2023, 10:54 p.m. UTC | #1
Hi Imre,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-dp-Fix-UHBR-link-M-N-values/20231114-043135
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20231113201110.510724-4-imre.deak%40intel.com
patch subject: [PATCH 4/4] drm/dp_mst: Fix PBN divider calculation for UHBR rates
config: i386-buildonly-randconfig-002-20231114 (https://download.01.org/0day-ci/archive/20231114/202311140620.1gHQRb4g-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231114/202311140620.1gHQRb4g-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311140620.1gHQRb4g-lkp@intel.com/

All errors (new ones prefixed by >>):

   ld: drivers/gpu/drm/display/drm_dp_mst_topology.o: in function `drm_dp_get_vc_payload_bw':
>> drm_dp_mst_topology.c:(.text+0x931): undefined reference to `__udivdi3'
kernel test robot Nov. 13, 2023, 11:05 p.m. UTC | #2
Hi Imre,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Imre-Deak/drm-i915-dp-Fix-UHBR-link-M-N-values/20231114-043135
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20231113201110.510724-4-imre.deak%40intel.com
patch subject: [PATCH 4/4] drm/dp_mst: Fix PBN divider calculation for UHBR rates
config: i386-randconfig-002-20231114 (https://download.01.org/0day-ci/archive/20231114/202311140621.sw31vG8M-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231114/202311140621.sw31vG8M-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202311140621.sw31vG8M-lkp@intel.com/

All errors (new ones prefixed by >>):

   ld: drivers/gpu/drm/display/drm_dp_mst_topology.o: in function `drm_dp_get_vc_payload_bw':
>> drivers/gpu/drm/display/drm_dp_mst_topology.c:3598: undefined reference to `__udivdi3'


vim +3598 drivers/gpu/drm/display/drm_dp_mst_topology.c

  3570	
  3571	/**
  3572	 * drm_dp_get_vc_payload_bw - get the VC payload BW for an MST link
  3573	 * @mgr: The &drm_dp_mst_topology_mgr to use
  3574	 * @link_rate: link rate in 10kbits/s units
  3575	 * @link_lane_count: lane count
  3576	 *
  3577	 * Calculate the total bandwidth of a MultiStream Transport link. The returned
  3578	 * value is in units of PBNs/(timeslots/1 MTP). This value can be used to
  3579	 * convert the number of PBNs required for a given stream to the number of
  3580	 * timeslots this stream requires in each MTP.
  3581	 */
  3582	int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
  3583				     int link_rate, int link_lane_count)
  3584	{
  3585		int ret;
  3586	
  3587		if (link_rate == 0 || link_lane_count == 0)
  3588			drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
  3589				    link_rate, link_lane_count);
  3590	
  3591		/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
  3592		/*
  3593		 * TODO: Return the value with a higher precision, allowing a better
  3594		 * slots per MTP allocation granularity. With the current returned
  3595		 * value +1 slot/MTP can get allocated on UHBR links.
  3596		 */
  3597		ret = mul_u32_u32(link_rate * link_lane_count,
> 3598				  drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate))) /
  3599		      (1000000ULL * 8 * 5400);
  3600	
  3601		return ret;
  3602	}
  3603	EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
  3604
diff mbox series

Patch

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 4d72c9a32026e..940a9fc0d0244 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3582,12 +3582,23 @@  static int drm_dp_send_up_ack_reply(struct drm_dp_mst_topology_mgr *mgr,
 int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
 			     int link_rate, int link_lane_count)
 {
+	int ret;
+
 	if (link_rate == 0 || link_lane_count == 0)
 		drm_dbg_kms(mgr->dev, "invalid link rate/lane count: (%d / %d)\n",
 			    link_rate, link_lane_count);
 
-	/* See DP v2.0 2.6.4.2, VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
-	return link_rate * link_lane_count / 54000;
+	/* See DP v2.0 2.6.4.2, 2.7.6.3 VCPayload_Bandwidth_for_OneTimeSlotPer_MTP_Allocation */
+	/*
+	 * TODO: Return the value with a higher precision, allowing a better
+	 * slots per MTP allocation granularity. With the current returned
+	 * value +1 slot/MTP can get allocated on UHBR links.
+	 */
+	ret = mul_u32_u32(link_rate * link_lane_count,
+			  drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate))) /
+	      (1000000ULL * 8 * 5400);
+
+	return ret;
 }
 EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
 
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index caee29d28463c..18ff6af0b5a31 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -251,6 +251,19 @@  drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
 	return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
 }
 
+/**
+ * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
+ * @link_rate: link rate in 10kbits/s units
+ *
+ * Determine if the provided link rate is an UHBR rate.
+ *
+ * Returns: %True if @link_rate is an UHBR rate.
+ */
+static inline bool drm_dp_is_uhbr_rate(int link_rate)
+{
+	return link_rate >= 1000000;
+}
+
 /*
  * DisplayPort AUX channel
  */