| Message ID | 20231122050206.3249424-1-shekhar.chauhan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Fix Wa_22016670082 | expand |
On Wed, Nov 22, 2023 at 10:32:06AM +0530, Shekhar Chauhan wrote: > Wa_22016670082 is applicable on GT and Media. > For GT, an MCR register is required instead of MMIO. > > Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 9de41703fae5..02d1d41fcfe1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -530,6 +530,7 @@ > #define GEN8_RC6_CTX_INFO _MMIO(0x8504) > > #define GEN12_SQCNT1 _MMIO(0x8718) > +#define SQCNT1 MCR_REG(0x8718) > #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) > #define GEN12_SQCNT1_OABPC REG_BIT(29) > #define GEN12_STRICT_RAR_ENABLE REG_BIT(23) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 9bc0654efdc0..34855e1ea1e6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > > /* Wa_22016670082 */ > - wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); > + wa_mcr_write_or(wal, SQCNT1, GEN12_STRICT_RAR_ENABLE); > > if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || > IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { > -- > 2.34.1 >
Hi Shekhar, > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Shekhar > Chauhan > Sent: Tuesday, November 21, 2023 9:02 PM > To: intel-gfx@lists.freedesktop.org > Cc: Roper, Matthew D <matthew.d.roper@intel.com> > Subject: [Intel-gfx] [PATCH] drm/i915/mtl: Fix Wa_22016670082 > > Wa_22016670082 is applicable on GT and Media. > For GT, an MCR register is required instead of MMIO. > > Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 9de41703fae5..02d1d41fcfe1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -530,6 +530,7 @@ > #define GEN8_RC6_CTX_INFO _MMIO(0x8504) > > #define GEN12_SQCNT1 _MMIO(0x8718) > +#define SQCNT1 MCR_REG(0x8718) SQCNT1 when defined stand alone, from a naming convention implies that this register with its current form is applicable to all the platforms supported by i915 driver, which clearly is not the case. From a naming perspective, I would suggest to use something on the lines of GEN12_GT_SQCNT1 for the MCR_REG. GEN12_SQCNT1 definition above should eventually be changed to MTL_MEDIA_SQCNT1 and all the places currently using GEN12_SQCNT1 should use the appropriate register access api's. Adding a TODO to the comment above will serve as a documentation for future and will be worthwhile to work on while this patch makes progress. Regards, Radhakrishna(RK) Sripada > #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) > #define GEN12_SQCNT1_OABPC REG_BIT(29) > #define GEN12_STRICT_RAR_ENABLE REG_BIT(23) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 9bc0654efdc0..34855e1ea1e6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct > i915_wa_list *wal) > wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); > > /* Wa_22016670082 */ > - wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); > + wa_mcr_write_or(wal, SQCNT1, GEN12_STRICT_RAR_ENABLE); > > if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || > IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) { > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 9de41703fae5..02d1d41fcfe1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -530,6 +530,7 @@ #define GEN8_RC6_CTX_INFO _MMIO(0x8504) #define GEN12_SQCNT1 _MMIO(0x8718) +#define SQCNT1 MCR_REG(0x8718) #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) #define GEN12_SQCNT1_OABPC REG_BIT(29) #define GEN12_STRICT_RAR_ENABLE REG_BIT(23) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 9bc0654efdc0..34855e1ea1e6 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1644,7 +1644,7 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); /* Wa_22016670082 */ - wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); + wa_mcr_write_or(wal, SQCNT1, GEN12_STRICT_RAR_ENABLE); if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
Wa_22016670082 is applicable on GT and Media. For GT, an MCR register is required instead of MMIO. Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)