From patchwork Thu Nov 23 04:27:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13465758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9787C61D85 for ; Thu, 23 Nov 2023 04:33:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A2B510E6CB; Thu, 23 Nov 2023 04:33:34 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9895810E0B1 for ; Thu, 23 Nov 2023 04:33:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700714009; x=1732250009; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xU95y4296/1bxSBkQpndVePWJNeNAIpEgT9y35+O5z8=; b=aEsX5BPPBJPXFObd9+OUZTwvenLU9MQwxR3i2aGbhZhLd8RNwmMBh62S lgM4Qz6ue5TBi3wBpeze45PssjxpACFQk5BSkSd5R7//i6OAYR8cStFGI RcHhoWJ/ojIyprCZjRmE27wGlz59mTrJtEeV90LaoUPzApKw04E7FRJCJ 31Qt/UztMxqh9kwelqczOFiCegpKBZGLpNiff07g6kRptqjtSd47evbb6 DrdPcZh6lJ+MEb+bTXVuChog7jvoPMGAqEQXTSE0nq8CCwfSNbP6q7Y/D Dg9qQCAY7x55A+Qth83icIe4+Mu/gIk3UQEwIagBOUkXGKgU1U/2Dv8ld g==; X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="5336589" X-IronPort-AV: E=Sophos;i="6.04,220,1695711600"; d="scan'208";a="5336589" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2023 20:33:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="796223331" X-IronPort-AV: E=Sophos;i="6.04,220,1695711600"; d="scan'208";a="796223331" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2023 20:33:27 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Nov 2023 09:57:32 +0530 Message-Id: <20231123042733.1027046-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231123042733.1027046-1-ankit.k.nautiyal@intel.com> References: <20231123042733.1027046-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dp_mst: Use helpers to get dsc min/max input bpc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use helpers for source min/max input bpc with DSC. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 2 -- drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++++------- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 37320cc4346f..0f5040c114b3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1622,7 +1622,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) { if (!HAS_DSC(i915)) @@ -2022,7 +2021,6 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); } -static u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) { /* Min DSC Input BPC for ICL+ is 8 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 05db46b111f2..931c5eb71cd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -184,5 +184,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, struct link_config_limits *limits); void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915); +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index d3d53e1b4489..337db31777df 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -293,17 +293,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, int i, num_bpc; u8 dsc_bpc[3] = {}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; - u8 dsc_max_bpc; + u8 dsc_max_bpc, dsc_min_bpc; int min_compressed_bpp, max_compressed_bpp; - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ - if (DISPLAY_VER(i915) >= 12) - dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); - else - dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); + dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp); - min_bpp = limits->pipe.min_bpp; + min_bpp = max_t(u8, dsc_min_bpc * 3, limits->pipe.min_bpp); num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);