diff mbox series

[1/7] drm/i915/display: Remove intel_crtc_state->psr_vsc

Message ID 20231214114838.1113648-2-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series VSC SDP rework | expand

Commit Message

Hogander, Jouni Dec. 14, 2023, 11:48 a.m. UTC
There is no really need to have separate vsc for psr usage. Use
intel_crtc_state->infoframes.vsc instead.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
 drivers/gpu/drm/i915/display/intel_psr.c           | 4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

Comments

Rodrigo Vivi Dec. 14, 2023, 4:26 p.m. UTC | #1
On Thu, Dec 14, 2023 at 01:48:32PM +0200, Jouni Högander wrote:
> There is no really need to have separate vsc for psr usage. Use
> intel_crtc_state->infoframes.vsc instead.

I was worried that this would mess with the regular dp path,
but then I noticed that that skips on has_psr, so

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 -
>  drivers/gpu/drm/i915/display/intel_psr.c           | 4 ++--
>  2 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 341d80c2b9de..a9c9b6edcc25 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1220,7 +1220,6 @@ struct intel_crtc_state {
>  	bool wm_level_disabled;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
> -	struct drm_dp_vsc_sdp psr_vsc;
>  
>  	/*
>  	 * Frequence the dpll for the port should run at. Differs from the
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b6e2e70e1290..9d5dc3fb6f20 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1380,7 +1380,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
>  	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> -				     &crtc_state->psr_vsc);
> +				     &crtc_state->infoframes.vsc);
>  }
>  
>  void intel_psr_get_config(struct intel_encoder *encoder,
> @@ -1652,7 +1652,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
>  			    intel_dp->psr.psr2_enabled ? "2" : "1");
>  
> -	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
> +	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->infoframes.vsc);
>  	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp, crtc_state);
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 341d80c2b9de..a9c9b6edcc25 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1220,7 +1220,6 @@  struct intel_crtc_state {
 	bool wm_level_disabled;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
-	struct drm_dp_vsc_sdp psr_vsc;
 
 	/*
 	 * Frequence the dpll for the port should run at. Differs from the
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b6e2e70e1290..9d5dc3fb6f20 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1380,7 +1380,7 @@  void intel_psr_compute_config(struct intel_dp *intel_dp,
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
-				     &crtc_state->psr_vsc);
+				     &crtc_state->infoframes.vsc);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1652,7 +1652,7 @@  static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 			    intel_dp->psr.psr2_enabled ? "2" : "1");
 
-	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
+	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->infoframes.vsc);
 	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp, crtc_state);