From patchwork Wed Dec 20 10:36:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13499929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8889C3DA6E for ; Wed, 20 Dec 2023 10:36:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C1BD10E55F; Wed, 20 Dec 2023 10:36:46 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id BAF4010E55A for ; Wed, 20 Dec 2023 10:36:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703068603; x=1734604603; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OSN2pQBPnxss1tPbPf81U73hlePGFYoWRPSoEF8oLa0=; b=XFXO70gqUJAwoFYRhD7xDEQIVLh+7Xe5z0uxiIYgc7zi3t67M/zO5cRg hqyxV7steya/grNt/HYryrsRd2J74bJe3aTF+ezqxdU+vGn270MnjmobI evOhHaE71stcRWgbhZnIbB5SBep5g6vQxjWWl6f0HBw6J2L1vBAK5ZGyh use9J/Ku40X5NSXXg0LUn/Df76JFYPNAk4pjHp/1kLwYn/YRD0P7D1Sb/ J8VNK1A2tFvICBMqpEY3S6gce8PqLNqHkCPF03OqoX9ZjZ0G5pJ6ckJTp s4WW/fgczCMQI5cGPgyzgL1xdtfBCimXfCEYab9vj/SxlSecOP6MXD39a A==; X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="2631998" X-IronPort-AV: E=Sophos;i="6.04,291,1695711600"; d="scan'208";a="2631998" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2023 02:36:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="1107686339" X-IronPort-AV: E=Sophos;i="6.04,291,1695711600"; d="scan'208";a="1107686339" Received: from sparrish-mobl1.amr.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.252.34.221]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2023 02:36:41 -0800 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 7/7] drm/i915/display: Take care of VSC select field in video dip ctl register Date: Wed, 20 Dec 2023 12:36:09 +0200 Message-Id: <20231220103609.1384523-8-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231220103609.1384523-1-jouni.hogander@intel.com> References: <20231220103609.1384523-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need to configure VSC Select field in video dip ctl if we want to have e.g. colorimetry date in our VSC SDP. Reported-by: Shawn Lee Signed-off-by: Jouni Högander Acked-by: Rodrigo Vivi Tested-by: Shawn Lee Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 39e4f5f7c817..eedef8121ff7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -523,10 +523,12 @@ void hsw_write_infoframe(struct intel_encoder *encoder, 0); /* Wa_14013475917 */ - if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC) - return; + if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)) + val |= hsw_infoframe_enable(type); + + if (type == DP_SDP_VSC) + val |= VSC_DIP_HW_DATA_SW_HEA; - val |= hsw_infoframe_enable(type); intel_de_write(dev_priv, ctl_reg, val); intel_de_posting_read(dev_priv, ctl_reg); }