diff mbox series

[1/2] drm/i915/display: No need for full modeset due to psr

Message ID 20240109100517.1947414-2-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series Allow PSR mode changes without full modeset | expand

Commit Message

Hogander, Jouni Jan. 9, 2024, 10:05 a.m. UTC 
There is no specific reason to force full modeset if psr is enabled.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Tested-by: Paz Zcharya <pazz@chromium.org>
---
 drivers/gpu/drm/i915/display/intel_display.c | 7 -------
 drivers/gpu/drm/i915/display/intel_dp.c      | 7 -------
 2 files changed, 14 deletions(-)

Comments

Lisovskiy, Stanislav Jan. 10, 2024, 12:54 p.m. UTC | #1 
On Tue, Jan 09, 2024 at 12:05:16PM +0200, Jouni Högander wrote:
> There is no specific reason to force full modeset if psr is enabled.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Tested-by: Paz Zcharya <pazz@chromium.org>


Reviewed-by: Stanislav Lisovskiy <staniskav.lisovskiy@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 7 -------
>  drivers/gpu/drm/i915/display/intel_dp.c      | 7 -------
>  2 files changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 31a6a82c1261..0cccf6df6718 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5202,13 +5202,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  		PIPE_CONF_CHECK_CSC(csc);
>  		PIPE_CONF_CHECK_CSC(output_csc);
> -
> -		if (current_config->active_planes) {
> -			PIPE_CONF_CHECK_BOOL(has_psr);
> -			PIPE_CONF_CHECK_BOOL(has_psr2);
> -			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> -			PIPE_CONF_CHECK_I(dc3co_exitline);
> -		}
>  	}
>  
>  	PIPE_CONF_CHECK_BOOL(double_wide);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7e4b7d5606d4..ab415f41924d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3326,13 +3326,6 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
>  		fastset = false;
>  	}
>  
> -	if (CAN_PSR(intel_dp)) {
> -		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
> -			    encoder->base.base.id, encoder->base.name);
> -		crtc_state->uapi.mode_changed = true;
> -		fastset = false;
> -	}
> -
>  	return fastset;
>  }
>  
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 31a6a82c1261..0cccf6df6718 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5202,13 +5202,6 @@  intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 		PIPE_CONF_CHECK_CSC(csc);
 		PIPE_CONF_CHECK_CSC(output_csc);
-
-		if (current_config->active_planes) {
-			PIPE_CONF_CHECK_BOOL(has_psr);
-			PIPE_CONF_CHECK_BOOL(has_psr2);
-			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-			PIPE_CONF_CHECK_I(dc3co_exitline);
-		}
 	}
 
 	PIPE_CONF_CHECK_BOOL(double_wide);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e4b7d5606d4..ab415f41924d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3326,13 +3326,6 @@  bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
 		fastset = false;
 	}
 
-	if (CAN_PSR(intel_dp)) {
-		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
-			    encoder->base.base.id, encoder->base.name);
-		crtc_state->uapi.mode_changed = true;
-		fastset = false;
-	}
-
 	return fastset;
 }