| Message ID | 20240123102850.390126-8-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Add Display Port tunnel BW allocation support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre > Deak > Sent: Tuesday, January 23, 2024 3:59 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org > Subject: [PATCH 07/19] drm/i915/dp: Factor out intel_dp_update_sink_caps() > > Factor out a function updating the sink's link rate and lane count capabilities, used > by a follow-up patch enabling the DP tunnel BW allocation mode. Looks good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++--- > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index f40706c5d1aad..23434d0aba188 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -3949,6 +3949,13 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp) > &intel_dp->desc); > } > > +void intel_dp_update_sink_caps(struct intel_dp *intel_dp) { > + intel_dp_set_sink_rates(intel_dp); > + intel_dp_set_max_sink_lane_count(intel_dp); > + intel_dp_set_common_rates(intel_dp); > +} > + > static bool > intel_dp_get_dpcd(struct intel_dp *intel_dp) { @@ -3965,9 +3972,7 @@ > intel_dp_get_dpcd(struct intel_dp *intel_dp) > drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, > drm_dp_is_branch(intel_dp->dpcd)); > > - intel_dp_set_sink_rates(intel_dp); > - intel_dp_set_max_sink_lane_count(intel_dp); > - intel_dp_set_common_rates(intel_dp); > + intel_dp_update_sink_caps(intel_dp); > } > > if (intel_dp_has_sink_count(intel_dp)) { diff --git > a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index a7906d8738c4a..49553e43add22 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -106,6 +106,7 @@ int intel_dp_config_required_rate(const struct > intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, > int rate); int intel_dp_max_common_rate(struct intel_dp *intel_dp); int > intel_dp_max_common_lane_count(struct intel_dp *intel_dp); > +void intel_dp_update_sink_caps(struct intel_dp *intel_dp); > > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, > u8 *link_bw, u8 *rate_select); > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f40706c5d1aad..23434d0aba188 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3949,6 +3949,13 @@ intel_dp_has_sink_count(struct intel_dp *intel_dp) &intel_dp->desc); } +void intel_dp_update_sink_caps(struct intel_dp *intel_dp) +{ + intel_dp_set_sink_rates(intel_dp); + intel_dp_set_max_sink_lane_count(intel_dp); + intel_dp_set_common_rates(intel_dp); +} + static bool intel_dp_get_dpcd(struct intel_dp *intel_dp) { @@ -3965,9 +3972,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd)); - intel_dp_set_sink_rates(intel_dp); - intel_dp_set_max_sink_lane_count(intel_dp); - intel_dp_set_common_rates(intel_dp); + intel_dp_update_sink_caps(intel_dp); } if (intel_dp_has_sink_count(intel_dp)) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a7906d8738c4a..49553e43add22 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -106,6 +106,7 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); int intel_dp_max_common_rate(struct intel_dp *intel_dp); int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); +void intel_dp_update_sink_caps(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select);
Factor out a function updating the sink's link rate and lane count capabilities, used by a follow-up patch enabling the DP tunnel BW allocation mode. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 11 ++++++++--- drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-)