| Message ID | 20240201085158.1000285-3-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Program Deep PKG_C_LATENCY register | expand |
> -----Original Message----- > From: Kandpal, Suraj <suraj.kandpal@intel.com> > Sent: Thursday, February 1, 2024 2:22 PM > To: intel-gfx@lists.freedesktop.org > Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Kandpal, > Suraj <suraj.kandpal@intel.com> > Subject: [PATCH 2/2] drm/i915/lnl: Program PKGC_LATENCY register > > Program the PKGC_LATENCY register with the highest latency from level 1 and > above LP registers else program with all 1's. > This is used to improve package C residency by sending the highest latency > tolerance requirement (LTR) when the planes are done with the frame until > the next frame programming window (set context latency, window 2) starts. > Bspec: 68986 > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 31 ++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index 051a02ac01a4..c07376f37baa 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3394,6 +3394,34 @@ static void skl_read_wm_latency(struct > drm_i915_private *i915, u16 wm[]) > adjust_wm_latency(i915, wm, num_levels, read_latency); } > > +/* > + * Program PKG_C_LATENCY Pkg C with highest valid latency from > + * watermark level1 and up and above. If watermark level 1 is > + * invalid program it with all 1's. > + * Program PKG_C_LATENCY Added Wake Time = 0. > + */ > +static void intel_program_pkgc_latency(struct drm_i915_private *i915, > + u16 wm_latency[]) > +{ > + u16 max_value = 0; > + u32 clear = 0, val = 0; > + int max_level = i915->display.wm.num_levels, i; > + > + for (i = 1; i <= max_level; i++) { > + if (wm_latency[i] == 0) > + break; > + else if (wm_latency[i] > max_value) Fix the indentation here. With the understanding that this is a bare bones implementation and pending work will be floated in a different series. LGTM Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > + max_value = wm_latency[i]; > + } > + > + if (max_value == 0) > + max_value = ~0 & LNL_PKG_C_LATENCY_MASK; > + > + clear |= LNL_ADDED_WAKE_TIME_MASK | > LNL_PKG_C_LATENCY_MASK; > + val |= max_value; > + intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); } > + > static void skl_setup_wm_latency(struct drm_i915_private *i915) { > if (HAS_HW_SAGV_WM(i915)) > @@ -3407,6 +3435,9 @@ static void skl_setup_wm_latency(struct > drm_i915_private *i915) > skl_read_wm_latency(i915, i915->display.wm.skl_latency); > > intel_print_wm_latency(i915, "Gen9 Plane", i915- > >display.wm.skl_latency); > + > + if (DISPLAY_VER(i915) >= 20) > + intel_program_pkgc_latency(i915, i915- > >display.wm.skl_latency); > } > > static const struct intel_wm_funcs skl_wm_funcs = { > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 051a02ac01a4..c07376f37baa 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3394,6 +3394,34 @@ static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) adjust_wm_latency(i915, wm, num_levels, read_latency); } +/* + * Program PKG_C_LATENCY Pkg C with highest valid latency from + * watermark level1 and up and above. If watermark level 1 is + * invalid program it with all 1's. + * Program PKG_C_LATENCY Added Wake Time = 0. + */ +static void intel_program_pkgc_latency(struct drm_i915_private *i915, + u16 wm_latency[]) +{ + u16 max_value = 0; + u32 clear = 0, val = 0; + int max_level = i915->display.wm.num_levels, i; + + for (i = 1; i <= max_level; i++) { + if (wm_latency[i] == 0) + break; + else if (wm_latency[i] > max_value) + max_value = wm_latency[i]; + } + + if (max_value == 0) + max_value = ~0 & LNL_PKG_C_LATENCY_MASK; + + clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; + val |= max_value; + intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); +} + static void skl_setup_wm_latency(struct drm_i915_private *i915) { if (HAS_HW_SAGV_WM(i915)) @@ -3407,6 +3435,9 @@ static void skl_setup_wm_latency(struct drm_i915_private *i915) skl_read_wm_latency(i915, i915->display.wm.skl_latency); intel_print_wm_latency(i915, "Gen9 Plane", i915->display.wm.skl_latency); + + if (DISPLAY_VER(i915) >= 20) + intel_program_pkgc_latency(i915, i915->display.wm.skl_latency); } static const struct intel_wm_funcs skl_wm_funcs = {
Program the PKGC_LATENCY register with the highest latency from level 1 and above LP registers else program with all 1's. This is used to improve package C residency by sending the highest latency tolerance requirement (LTR) when the planes are done with the frame until the next frame programming window (set context latency, window 2) starts. Bspec: 68986 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/skl_watermark.c | 31 ++++++++++++++++++++ 1 file changed, 31 insertions(+)