| Message ID | 20240209183809.16887-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: PLL state check stuff | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala > Sent: Friday, February 9, 2024 8:38 PM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH 3/5] drm/i915: Reuse ibx_dump_hw_state() for gmch platforms > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > GMCH platform DPLLs are similar to the IBX+ PCH DPLLs so we can just use the same state dump function for both. > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index e7e0a4cf9f93..c6cc7465b92c 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -4458,13 +4458,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915, > /* fallback for platforms that don't use the shared dpll > * infrastructure > */ > - drm_dbg_kms(&i915->drm, > - "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " > - "fp0: 0x%x, fp1: 0x%x\n", > - hw_state->dpll, > - hw_state->dpll_md, > - hw_state->fp0, > - hw_state->fp1); > + ibx_dump_hw_state(i915, hw_state); > } > } > > -- > 2.43.0
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e7e0a4cf9f93..c6cc7465b92c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -4458,13 +4458,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915, /* fallback for platforms that don't use the shared dpll * infrastructure */ - drm_dbg_kms(&i915->drm, - "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + ibx_dump_hw_state(i915, hw_state); } }