| Message ID | 20240220121045.2156004-6-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ALPM AUX-Less | expand |
Hi Jouni, kernel test robot noticed the following build warnings: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip drm/drm-next next-20240221] [cannot apply to drm-intel/for-linux-next-fixes linus/master v6.8-rc5] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Jouni-H-gander/drm-display-Add-missing-aux-less-alpm-wake-related-bits/20240220-201356 base: git://anongit.freedesktop.org/drm-intel for-linux-next patch link: https://lore.kernel.org/r/20240220121045.2156004-6-jouni.hogander%40intel.com patch subject: [PATCH v2 5/6] drm/i915/psr: Enable ALPM for eDP Panel replay config: riscv-allmodconfig (https://download.01.org/0day-ci/archive/20240222/202402220225.2eViN531-lkp@intel.com/config) compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project 36adfec155de366d722f2bac8ff9162289dcf06c) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240222/202402220225.2eViN531-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202402220225.2eViN531-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/gpu/drm/i915/display/intel_psr.c:1705:3: warning: variable 'alpm_ctl' is uninitialized when used here [-Wuninitialized] 1705 | alpm_ctl |= ALPM_CTL_ALPM_ENABLE | | ^~~~~~~~ drivers/gpu/drm/i915/display/intel_psr.c:1699:14: note: initialize the variable 'alpm_ctl' to silence this warning 1699 | u32 alpm_ctl; | ^ | = 0 1 warning generated. vim +/alpm_ctl +1705 drivers/gpu/drm/i915/display/intel_psr.c 1693 1694 static void lnl_alpm_configure(struct intel_dp *intel_dp) 1695 { 1696 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1697 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1698 struct intel_psr *psr = &intel_dp->psr; 1699 u32 alpm_ctl; 1700 1701 if (DISPLAY_VER(dev_priv) < 20) 1702 return; 1703 1704 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { > 1705 alpm_ctl |= ALPM_CTL_ALPM_ENABLE | 1706 ALPM_CTL_ALPM_AUX_LESS_ENABLE | 1707 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; 1708 1709 intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder), 1710 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | 1711 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | 1712 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | 1713 PORT_ALPM_CTL_SILENCE_PERIOD( 1714 psr->alpm_parameters.silence_period_sym_clocks)); 1715 1716 intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder), 1717 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | 1718 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( 1719 psr->alpm_parameters.lfps_half_cycle_num_of_syms) | 1720 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( 1721 psr->alpm_parameters.lfps_half_cycle_num_of_syms) | 1722 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( 1723 psr->alpm_parameters.lfps_half_cycle_num_of_syms)); 1724 } else { 1725 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | 1726 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines); 1727 } 1728 1729 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines); 1730 1731 intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl); 1732 } 1733
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a269e3c10db9..bf410c4890f4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1696,14 +1696,39 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; struct intel_psr *psr = &intel_dp->psr; + u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20) return; - intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), - ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | - ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines) | - ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines)); + if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { + alpm_ctl |= ALPM_CTL_ALPM_ENABLE | + ALPM_CTL_ALPM_AUX_LESS_ENABLE | + ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; + + intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder), + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | + PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | + PORT_ALPM_CTL_SILENCE_PERIOD( + psr->alpm_parameters.silence_period_sym_clocks)); + + intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder), + PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | + PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( + psr->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( + psr->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( + psr->alpm_parameters.lfps_half_cycle_num_of_syms)); + } else { + alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | + ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines); + } + + alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines); + + intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl); } static void intel_psr_enable_source(struct intel_dp *intel_dp, @@ -1974,6 +1999,15 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_snps_phy_update_psr_power_state(dev_priv, phy, false); + if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { + intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder), + ALPM_CTL_ALPM_ENABLE | + ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); + + intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder), + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); + } + /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);