From patchwork Wed Feb 21 12:13:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13565498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2A2BC48BC3 for ; Wed, 21 Feb 2024 12:20:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3DB7710E71E; Wed, 21 Feb 2024 12:20:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="YbLn2rtN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7029110E720 for ; Wed, 21 Feb 2024 12:20:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708518024; x=1740054024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BQ/eRLgSchQT12BmgqlLX+MFPTfIGvn7NMF6EVApFNo=; b=YbLn2rtNj0M+MNa+Tb2iwYoqXSKqiNUVjg9E7q7DF/YaMzTZgAhyeQKr k2wlgQegC8/rsmXhwTK7VvXXK3JMHeX5nwNFkrZUyliJSeF/cQRj0nNpQ TAESeRqg62bOC9d1muX8vacfL7NJOVul3Hvc2lm+VxhBGqDR4zVbDou1e 8JQASBSq0O/+QZQ2YGtQKEczyqWnXVVZw1xjIohYZc93vPpuU9LCCROgP P2DTW73NaB1Jvk3O2rHL4W2ImV1JQj5GOpnCf3mrA0fGkPIl0oYOLsmua 1phuK40UMW+lIsnDZdetVhjzEPYEUD8otVV6YT/chJdtrZfutCsmiAlsX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10990"; a="6488811" X-IronPort-AV: E=Sophos;i="6.06,175,1705392000"; d="scan'208";a="6488811" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2024 04:20:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,175,1705392000"; d="scan'208";a="5426137" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 21 Feb 2024 04:20:21 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, Mitul Golani Subject: [PATCH 5/6] drm/i915/display: Compute vrr_vsync params Date: Wed, 21 Feb 2024 17:43:20 +0530 Message-Id: <20240221121321.2213128-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240221121321.2213128-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240221121321.2213128-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute vrr_vsync_start/end which sets the position for hardware to send the Vsync at a fixed position relative to the end of the Vblank. --v2: - Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit) - Update bit fields of VRR_VSYNC_START/END.(Ankit) Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 12 ++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ 4 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 00ac65a14029..5994f7fcbb6a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5321,6 +5321,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.flipline); PIPE_CONF_CHECK_I(vrr.pipeline_full); PIPE_CONF_CHECK_I(vrr.guardband); + PIPE_CONF_CHECK_BOOL(vrr.as_sdp_enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 93b4b7dff1d0..7859e4baad4b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1416,6 +1416,7 @@ struct intel_crtc_state { u16 flipline, vmin, vmax, guardband; u8 as_sdp_mode; bool as_sdp_enable; + u32 vsync_end, vsync_start; } vrr; /* Stream Splitter for eDP MSO */ diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 08e3ba69bd30..29ddf504d94b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -150,6 +150,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; + crtc_state->vrr.vsync_start = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + VRR_VSYNC_START(crtc_state->hw.adjusted_mode.vsync_start)); + crtc_state->vrr.vsync_end = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + (VRR_VSYNC_END(crtc_state->hw.adjusted_mode.vsync_end) >> 16)); + /* * For XE_LPD+, we use guardband and pipeline override * is deprecated. @@ -273,8 +280,13 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) u32 trans_vrr_ctl; trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); + bool as_sdp_enabled = + intel_de_read(dev_priv, + HSW_TVIDEO_DIP_CTL(cpu_transcoder)); crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + crtc_state->vrr.as_sdp_enable = + as_sdp_enabled & VIDEO_DIP_ENABLE_ADAPTIVE_SYNC; if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c02ea07af4c2..3e0853458ef4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2007,7 +2007,9 @@ #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 +#define _TRANS_VRR_VSYNC_A 0x60078 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) @@ -2087,6 +2089,11 @@ #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end)) +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start)) + #define _TRANS_PUSH_A 0x60A70 #define _TRANS_PUSH_B 0x61A70 #define _TRANS_PUSH_C 0x62A70