From patchwork Wed Feb 28 14:14:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13575598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D95DC54E49 for ; Wed, 28 Feb 2024 14:21:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BBFC10E82F; Wed, 28 Feb 2024 14:21:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JW4Mg2cP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id E627A10E771; Wed, 28 Feb 2024 14:21:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709130077; x=1740666077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l8wW4BFy7UHEYsdHX3DNsBLprplcW8NPmSPaVEnAK5o=; b=JW4Mg2cPNF9BGHNrfIjbB4huN7WXLrIf7Z9irD92gSbviUay+eTVrbN3 sGbX/W1gwOgPXO2m2RKypwxdqQsvlMBBD5riD4IohvS4C1LKOIxPqT/Ib jemeqQYoo99aLaPEWywnG1MhJ7PxZW8m6VTzkpL+BULGlCTB3Rv27e+Ts XglJlcylOCn3/QV0Zey5frplOxbYtZwBdguNuaL4cTVz4TBfH4fq01gxH wD/ftt5+RRO4krGcbvWxeZ69Rc3BRWaQH7Kg4Dx/8wAAETRO7el/9e8hI eqY+OR4lQmR5HPBCJH3Xb5Er7h/KGHMBbkQNMnoTmZH3OTQ/qmCPj1Dkw g==; X-IronPort-AV: E=McAfee;i="6600,9927,10998"; a="14080561" X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="14080561" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 06:21:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="7488167" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa009.jf.intel.com with ESMTP; 28 Feb 2024 06:21:14 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, ankit.k.nautiyal@intel.com, Mitul Golani Subject: [PATCH v11 8/8] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Date: Wed, 28 Feb 2024 19:44:12 +0530 Message-Id: <20240228141412.2761101-9-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240228141412.2761101-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240228141412.2761101-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Write/Read Adaptive sync SDP only when Sink and Source is enabled for the same. Also along with write TRANS_VRR_VSYNC values. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bea441590204..89b8d50f12c6 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); /* XXX: DSI transcoder paranoia */ if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) @@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); + if (intel_dp_as_sdp_supported(intel_dp)) + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); + intel_audio_codec_get_config(encoder, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2ec1f923a5a0..8304ef912767 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4276,6 +4276,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL; u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */ if (!enable && HAS_DSC(dev_priv)) @@ -4293,6 +4294,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + if (intel_dp_as_sdp_supported(intel_dp)) + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 668927524f23..d24a42902e69 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -214,6 +214,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); + + if (crtc_state->vrr.vsync_end && crtc_state->vrr.vsync_start) + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), + crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start); } void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)