From patchwork Thu Feb 29 16:25:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mitul Golani X-Patchwork-Id: 13577380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 231E7C54E49 for ; Thu, 29 Feb 2024 16:32:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB24310E551; Thu, 29 Feb 2024 16:32:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UbvmkgwM"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 951E010E543; Thu, 29 Feb 2024 16:32:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709224344; x=1740760344; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IQkVPAF82fASgK+ib8YG3Bz8sMHPusteHEGWCSjG764=; b=UbvmkgwMbiem+HBTIkq9YEM5vLgnMj+RncUDsvyVk9KX7fr7hEHIvSCm Ao5CIKBx6b30r8DbthxITeD6/OWWpts3q1ow9pibP0MSEjeV5Q4C3QwfS uV3dmHXHBVcOKUEMjdGROhuI2ZDU36ycZdyQ6AV7HbxLMEm4uiTY8n1k4 javcVBcoWH2kA81vy8HMZthLEbi0OsUenWr+88XE6gwvAWOx32TY9Yoic bNGvKNFozzXNuhx9UN/HLff9DEqt1KMv8SKd4KTIP/w+ZCH9gESRlFfzg 3BU/yIXtWCqMo1o3aRhkMgnZkOiMdKJGQmqQJwLwsZk/432Jp0UGQXQ+/ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10999"; a="29137252" X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208";a="29137252" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Feb 2024 08:32:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,194,1705392000"; d="scan'208";a="7754373" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by fmviesa007.fm.intel.com with ESMTP; 29 Feb 2024 08:32:16 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, ankit.k.nautiyal@intel.com, Mitul Golani Subject: [PATCH v13 5/8] drm/i915/display: Compute AS SDP parameters Date: Thu, 29 Feb 2024 21:55:18 +0530 Message-Id: <20240229162521.2943630-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240229162521.2943630-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240229162521.2943630-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add necessary function definitions to compute AS SDP data. The new intel_dp_compute_as_sdp function computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR). --v2: - Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit] - Separated patch for intel_read/write_dp_sdp. [Ankit] - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit] - Fixed indentation issues. [Ankit] --v3: - Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. --v4: - Added HAS_VRR check before writing AS SDP. --v5: Added missed HAS_VRR check before reading AS SDP. --v6: - Used Adaptive Sync sink status as a check for read/write SDP. (Ankit) --v7: - Remove as_sdp_enable from crtc_state. - Add a comment mentioning current support of DP_AS_SDP_AVT_FIXED_VTOTAL. - Add state checker for AS_SDP infoframe enable. --v8: - Drop conn_state from intel_dp_compute_as_sdp, as not used. - Remove fullstop in subject line. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b26efce4a041..86de854516ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2626,6 +2626,31 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; } +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int vrefresh = drm_mode_vrefresh(adjusted_mode); + + if (!intel_vrr_is_in_range(connector, vrefresh) || + !intel_dp_as_sdp_supported(intel_dp)) + return; + + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); + + /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; + as_sdp->length = 0x9; + as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = 0; + as_sdp->duration_incr_ms = 0; + as_sdp->duration_incr_ms = 0; +} + static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -2951,6 +2976,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, g4x_dp_set_clock(encoder, pipe_config); intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_compute_as_sdp(intel_dp, pipe_config); intel_psr_compute_config(intel_dp, pipe_config, conn_state); intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);