diff mbox series

[v3,2/4] drm/i915/gt: Do not exposed fused off engines.

Message ID 20240229232859.70058-3-andi.shyti@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Disable automatic load CCS load balancing | expand

Commit Message

Andi Shyti Feb. 29, 2024, 11:28 p.m. UTC
Some of the CCS engines are disabled. They should not be listed
in the uabi_engine list, that is the list of engines that the
user can see.

Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Requires: 4e4f77d74878 ("drm/i915/gt: Refactor uabi engine class/instance list creation")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_user.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Matt Roper March 5, 2024, 9:52 p.m. UTC | #1
On Fri, Mar 01, 2024 at 12:28:57AM +0100, Andi Shyti wrote:
> Some of the CCS engines are disabled. They should not be listed
> in the uabi_engine list, that is the list of engines that the
> user can see.

Fused off engines already aren't visible to userspace (or to the kernel
for that matter).  For CCS engines engine_mask_apply_compute_fuses()
removes the fused off engines from the runtime engine mask; other engine
types are handled in similar functions.  Any engine that doesn't appear
in the filtered down engine_mask won't even have a 'struct
intel_engine_cs' allocated for it.


Matt

> 
> Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
> Requires: 4e4f77d74878 ("drm/i915/gt: Refactor uabi engine class/instance list creation")
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_user.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index cf8f24ad88f6..ec5bcd1c1ec4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -244,6 +244,18 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
>  		if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
>  			continue;
>  
> +		/*
> +		 * If the CCS engine is fused off, the corresponding bit
> +		 * in the engine mask is disabled. Do not expose it
> +		 * to the user.
> +		 *
> +		 * By default at least one engine is enabled (check
> +		 * the engine_mask_apply_compute_fuses() function.
> +		 */
> +		if (!(engine->gt->info.engine_mask &
> +		      BIT(_CCS(engine->uabi_instance))))
> +			continue;
> +
>  		GEM_BUG_ON(uabi_class >=
>  			   ARRAY_SIZE(i915->engine_uabi_class_count));
>  		i915->engine_uabi_class_count[uabi_class]++;
> -- 
> 2.43.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index cf8f24ad88f6..ec5bcd1c1ec4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -244,6 +244,18 @@  void intel_engines_driver_register(struct drm_i915_private *i915)
 		if (uabi_class > I915_LAST_UABI_ENGINE_CLASS)
 			continue;
 
+		/*
+		 * If the CCS engine is fused off, the corresponding bit
+		 * in the engine mask is disabled. Do not expose it
+		 * to the user.
+		 *
+		 * By default at least one engine is enabled (check
+		 * the engine_mask_apply_compute_fuses() function.
+		 */
+		if (!(engine->gt->info.engine_mask &
+		      BIT(_CCS(engine->uabi_instance))))
+			continue;
+
 		GEM_BUG_ON(uabi_class >=
 			   ARRAY_SIZE(i915->engine_uabi_class_count));
 		i915->engine_uabi_class_count[uabi_class]++;