| Message ID | 20240313143825.3461208-1-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/scaler: Update Pipe src size check in skl_update_scaler | expand |
On Wed, Mar 13, 2024 at 08:08:25PM +0530, Ankit Nautiyal wrote: > For Earlier platforms, the Pipe source size is 12-bits so > max pipe source width and height is 4096. For newer platforms it is > 13-bits so theoretically max width/height is 8192. For few of the > earlier platforms the scaler did not use all bits of the PIPESRC, > so max scaler source size was used to make that the pipe source > size is programmed within limits, before using scaler. > > This creates a problem, for MTL where scaler source size is 4096, but > max pipe source width can theroretically be 8192. > > Switch the check to use the max scaler destination size, which closely > match the limits. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/skl_scaler.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c > index 8a934bada624..baa601d27815 100644 > --- a/drivers/gpu/drm/i915/display/skl_scaler.c > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c > @@ -213,10 +213,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, > * The pipe scaler does not use all the bits of PIPESRC, at least > * on the earlier platforms. So even when we're scaling a plane > * the *pipe* source size must not be too large. For simplicity > - * we assume the limits match the scaler source size limits. Might > - * not be 100% accurate on all platforms, but good enough for now. > + * we assume the limits match the scaler destination size limits. > + * Might not be 100% accurate on all platforms, but good enough for > + * now. > */ > - if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) { > + if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { > drm_dbg_kms(&dev_priv->drm, > "scaler_user index %u.%u: pipe src size %ux%u " > "is out of scaler range\n", > -- > 2.40.1
On 3/15/2024 1:56 PM, Ville Syrjälä wrote: > On Wed, Mar 13, 2024 at 08:08:25PM +0530, Ankit Nautiyal wrote: >> For Earlier platforms, the Pipe source size is 12-bits so >> max pipe source width and height is 4096. For newer platforms it is >> 13-bits so theoretically max width/height is 8192. For few of the >> earlier platforms the scaler did not use all bits of the PIPESRC, >> so max scaler source size was used to make that the pipe source >> size is programmed within limits, before using scaler. >> >> This creates a problem, for MTL where scaler source size is 4096, but >> max pipe source width can theroretically be 8192. >> >> Switch the check to use the max scaler destination size, which closely >> match the limits. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Thanks for the review, pushed to drm-intel-next. Regards, Ankit > >> --- >> drivers/gpu/drm/i915/display/skl_scaler.c | 7 ++++--- >> 1 file changed, 4 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c >> index 8a934bada624..baa601d27815 100644 >> --- a/drivers/gpu/drm/i915/display/skl_scaler.c >> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c >> @@ -213,10 +213,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, >> * The pipe scaler does not use all the bits of PIPESRC, at least >> * on the earlier platforms. So even when we're scaling a plane >> * the *pipe* source size must not be too large. For simplicity >> - * we assume the limits match the scaler source size limits. Might >> - * not be 100% accurate on all platforms, but good enough for now. >> + * we assume the limits match the scaler destination size limits. >> + * Might not be 100% accurate on all platforms, but good enough for >> + * now. >> */ >> - if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) { >> + if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { >> drm_dbg_kms(&dev_priv->drm, >> "scaler_user index %u.%u: pipe src size %ux%u " >> "is out of scaler range\n", >> -- >> 2.40.1
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 8a934bada624..baa601d27815 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -213,10 +213,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, * The pipe scaler does not use all the bits of PIPESRC, at least * on the earlier platforms. So even when we're scaling a plane * the *pipe* source size must not be too large. For simplicity - * we assume the limits match the scaler source size limits. Might - * not be 100% accurate on all platforms, but good enough for now. + * we assume the limits match the scaler destination size limits. + * Might not be 100% accurate on all platforms, but good enough for + * now. */ - if (pipe_src_w > max_src_w || pipe_src_h > max_src_h) { + if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: pipe src size %ux%u " "is out of scaler range\n",
For Earlier platforms, the Pipe source size is 12-bits so max pipe source width and height is 4096. For newer platforms it is 13-bits so theoretically max width/height is 8192. For few of the earlier platforms the scaler did not use all bits of the PIPESRC, so max scaler source size was used to make that the pipe source size is programmed within limits, before using scaler. This creates a problem, for MTL where scaler source size is 4096, but max pipe source width can theroretically be 8192. Switch the check to use the max scaler destination size, which closely match the limits. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/skl_scaler.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)