From patchwork Tue Apr 2 15:50:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13614357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3418CD1284 for ; Tue, 2 Apr 2024 15:50:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C7DD10FE11; Tue, 2 Apr 2024 15:50:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Rh6lEpio"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9F6ED10FE11 for ; Tue, 2 Apr 2024 15:50:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712073035; x=1743609035; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zo5IwB/aUWvPaC3Q0fD4zQGfi0/OVt4td8NDZ5kCzRY=; b=Rh6lEpioGF384gRBZVU6ii/FdCU/xQfJFlhurDFqejTn25Q0aLnCHiEg N/gs04OsxZqgRO07Dk+zJMq7qZD+pXYzW50Zs2NGm4WaopGq1SyofZDJv ZRJPjxn8puecwGBEyucz/Zbj8HcfuLnbi593qcM5hJlLhYZKw6kYf+qW4 JXWJ0IkIPKYXLiBZ5VYheQzeIAaq7IaH4Il7uXV1Jlpgcr6PCPBdyRUhY amTU/vccEAWEOxx2DrVa6AUZaBTVtaQaeAxquo/zpu/VVI3pB81ME+byH /8teTFO3UPfuQkRVxP/2xViD6hLhECKHzMUBcG7uGS0Z1YPKfiL/VAfGL Q==; X-CSE-ConnectionGUID: aAdvPVVcS+WvM2fsnqoZew== X-CSE-MsgGUID: 5xm84XKnQCmUrgNURp9hDw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="17980831" X-IronPort-AV: E=Sophos;i="6.07,175,1708416000"; d="scan'208";a="17980831" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2024 08:50:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="827789471" X-IronPort-AV: E=Sophos;i="6.07,175,1708416000"; d="scan'208";a="827789471" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orsmga001.jf.intel.com with SMTP; 02 Apr 2024 08:50:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 02 Apr 2024 18:50:32 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: Uma Shankar Subject: [PATCH v2 05/14] drm/i915: Loop over all active pipes in intel_mbus_dbox_update Date: Tue, 2 Apr 2024 18:50:07 +0300 Message-ID: <20240402155016.13733-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240402155016.13733-1-ville.syrjala@linux.intel.com> References: <20240402155016.13733-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Stanislav Lisovskiy We need to loop through all active pipes, not just the ones, that are in current state, because disabling and enabling even a particular pipe affects credits in another one. Reviewed-by: Uma Shankar Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_watermark.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index bc341abcab2f..f582992592c1 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3680,10 +3680,8 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; - const struct intel_crtc_state *new_crtc_state; const struct intel_crtc *crtc; u32 val = 0; - int i; if (DISPLAY_VER(i915) < 11) return; @@ -3727,12 +3725,9 @@ void intel_mbus_dbox_update(struct intel_atomic_state *state) val |= MBUS_DBOX_B_CREDIT(8); } - for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { u32 pipe_val = val; - if (!new_crtc_state->hw.active) - continue; - if (DISPLAY_VER(i915) >= 14) { if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, new_dbuf_state->active_pipes))