From patchwork Wed Apr 24 18:38:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13642393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D095C4345F for ; Wed, 24 Apr 2024 18:54:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FDF8113D42; Wed, 24 Apr 2024 18:54:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="XAYi3ybS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35D2B113D3E; Wed, 24 Apr 2024 18:54:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713984847; x=1745520847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KeNY3lnx+UHQDcoTB3ACEAUH9oN1ukBRejKjXq8LeW8=; b=XAYi3ybSA/ZIx963XcHHqo2obA13cj6xSwWcGEJ3BEwkPgCLSP9zm5f0 Xc/88XKXVbCU53BM/rkFK1fQ+uUxrvh9wy9lgtdf6OKKoiVu7xOOqz8Ii j/9N4QcT40bmstOELVvlYZaiTAN3CQBpZchsnrembna9pW0gjz32lkWBD wesf6KbYrGfh1Pcv5SNIls371qddWmYbVceyZRqf+b+HxIbgzgVTcYe3B KRzde7V95rrcoOsGQklaJTL4OwGxD296vUMSi5EGNXUpQ8U4JJLJb8N9v xB8Ao4Xs8IqRA+gLpRVqnJu7g4Qu8IwYv6Xxxc/JE1I8JbGhI1yV8PB3s g==; X-CSE-ConnectionGUID: 0U+Ic7TCTjWHw4rTE4zJdg== X-CSE-MsgGUID: MY+6DY+kQOiPB8IS1pL85g== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="21061115" X-IronPort-AV: E=Sophos;i="6.07,227,1708416000"; d="scan'208";a="21061115" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:54:07 -0700 X-CSE-ConnectionGUID: pyl7Uh7mSKCsVQETfX8Z+Q== X-CSE-MsgGUID: wQGwrgU7TvWHst5xDk68Bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,227,1708416000"; d="scan'208";a="25240501" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orviesa006.jf.intel.com with ESMTP; 24 Apr 2024 11:54:06 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, jani.nikula@intel.com, jouni.hogander@intel.com, arun.r.murthy@intel.com Subject: [PATCH v3 3/6] drm/display: Add missing aux less alpm wake related bits Date: Thu, 25 Apr 2024 00:08:17 +0530 Message-Id: <20240424183820.3591593-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20240424183820.3591593-1-animesh.manna@intel.com> References: <20240424183820.3591593-1-animesh.manna@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Jouni Högander eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Signed-off-by: Jouni Högander --- include/drm/display/drm_dp.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 0b032faa8cf2..ad0cb0a1de87 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -677,7 +679,8 @@ #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE (1 << 0) -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)