| Message ID | 20240502044057.896348-2-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI | expand |
> -----Original Message----- > From: Kandpal, Suraj <suraj.kandpal@intel.com> > Sent: Thursday, May 2, 2024 10:11 AM > To: intel-gfx@lists.freedesktop.org > Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Shankar, > Uma <uma.shankar@intel.com>; Nautiyal, Ankit K > <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com> > Subject: [PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on > HDMI > > Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI > TMDS operation for DISPLAY_VER >= 14. > > --v2 > -Wa to be mentioned in comments not in commit message [Jani] -Remove > blankline [Jani] > > --v3 > -No need to write what is being done in comments when code is self > explanatory [Jani] > > --v4 > -Add comment regarding need of this WA when in TMDS mode [Chaitanya] - > Write in chicken register for MTL [CHaitanya] > > --v5 > -Fix comment [Chaitanya] > -Use correct set and clear value in intel_de_rmw [Chaitanya] > > Bspec: 49273 > Bspec: 69964 LGTM Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c > b/drivers/gpu/drm/i915/display/intel_hdcp.c > index d5ed4c7dfbc0..02cbbbfd8e25 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -30,6 +30,27 @@ > #define KEY_LOAD_TRIES 5 > #define HDCP2_LC_RETRY_CNT 3 > > +/* WA: 16022217614 */ > +static void > +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, > + struct intel_hdcp *hdcp) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > + /* Here we assume HDMI is in TMDS mode of operation */ > + if (encoder->type != INTEL_OUTPUT_HDMI) > + return; > + > + if (DISPLAY_VER(dev_priv) >= 14) { > + if (IS_METEORLAKE(dev_priv)) > + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp- > >cpu_transcoder), > + 0, HDCP_LINE_REKEY_DISABLE); > + else > + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp- > >cpu_transcoder), > + 0, > TRANS_DDI_HDCP_LINE_REKEY_DISABLE); > + } > +} > + > static int intel_conn_to_vcpi(struct intel_atomic_state *state, > struct intel_connector *connector) { @@ -2005,6 > +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state, > connector->base.base.id, connector->base.name, > hdcp->content_type); > > + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); > + > ret = hdcp2_authenticate_and_encrypt(state, connector); > if (ret) { > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. > (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h index e22a82a5ddd7..31338d825e34 > 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3501,6 +3501,8 @@ > [TRANSCODER_D] = > _CHICKEN_TRANS_D)) > #define _MTL_CHICKEN_TRANS_A 0x604e0 > #define _MTL_CHICKEN_TRANS_B 0x614e0 > +#define _MTL_CHICKEN_TRANS_C 0x624e0 > +#define _MTL_CHICKEN_TRANS_D 0x634e0 > #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ > _MTL_CHICKEN_TRANS_A, > \ > _MTL_CHICKEN_TRANS_B) > @@ -3519,6 +3521,7 @@ > #define DP_FEC_BS_JITTER_WA REG_BIT(15) > #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) > #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) > +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) > > #define DISP_ARB_CTL _MMIO(0x45000) > #define DISP_FBC_MEMORY_WAKE REG_BIT(31) > @@ -4520,6 +4523,7 @@ enum skl_power_gate { > #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) > #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) > #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) > +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) > #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, > 10) > #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ > REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, > trans) > -- > 2.43.2
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj > Kandpal > Sent: Thursday, May 2, 2024 10:11 AM > To: intel-gfx@lists.freedesktop.org > Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Shankar, > Uma <uma.shankar@intel.com>; Nautiyal, Ankit K > <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com> > Subject: [PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on > HDMI > > Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI > TMDS operation for DISPLAY_VER >= 14. > > --v2 > -Wa to be mentioned in comments not in commit message [Jani] -Remove > blankline [Jani] > > --v3 > -No need to write what is being done in comments when code is self > explanatory [Jani] > > --v4 > -Add comment regarding need of this WA when in TMDS mode [Chaitanya] - > Write in chicken register for MTL [CHaitanya] > > --v5 > -Fix comment [Chaitanya] > -Use correct set and clear value in intel_de_rmw [Chaitanya] > > Bspec: 49273 > Bspec: 69964 > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 27 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c > b/drivers/gpu/drm/i915/display/intel_hdcp.c > index d5ed4c7dfbc0..02cbbbfd8e25 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -30,6 +30,27 @@ > #define KEY_LOAD_TRIES 5 > #define HDCP2_LC_RETRY_CNT 3 > > +/* WA: 16022217614 */ > +static void > +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, > + struct intel_hdcp *hdcp) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > + /* Here we assume HDMI is in TMDS mode of operation */ > + if (encoder->type != INTEL_OUTPUT_HDMI) > + return; > + > + if (DISPLAY_VER(dev_priv) >= 14) { > + if (IS_METEORLAKE(dev_priv)) > + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp- > >cpu_transcoder), > + 0, HDCP_LINE_REKEY_DISABLE); > + else > + intel_de_rmw(dev_priv, > TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), > + 0, > TRANS_DDI_HDCP_LINE_REKEY_DISABLE); > + } > +} > + > static int intel_conn_to_vcpi(struct intel_atomic_state *state, > struct intel_connector *connector) { @@ -2005,6 > +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state, > connector->base.base.id, connector->base.name, > hdcp->content_type); > > + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); > + > ret = hdcp2_authenticate_and_encrypt(state, connector); > if (ret) { > drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. > (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h index e22a82a5ddd7..31338d825e34 > 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3501,6 +3501,8 @@ > [TRANSCODER_D] = > _CHICKEN_TRANS_D)) > #define _MTL_CHICKEN_TRANS_A 0x604e0 > #define _MTL_CHICKEN_TRANS_B 0x614e0 > +#define _MTL_CHICKEN_TRANS_C 0x624e0 > +#define _MTL_CHICKEN_TRANS_D 0x634e0 No need of macro for transcoder c and d, as per transcoder it will be calculated by _MMIO_TRANS((trans). Regards, Animesh > #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ > _MTL_CHICKEN_TRANS_A, > \ > _MTL_CHICKEN_TRANS_B) > @@ -3519,6 +3521,7 @@ > #define DP_FEC_BS_JITTER_WA REG_BIT(15) > #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) > #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) > +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) > > #define DISP_ARB_CTL _MMIO(0x45000) > #define DISP_FBC_MEMORY_WAKE REG_BIT(31) > @@ -4520,6 +4523,7 @@ enum skl_power_gate { > #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) > #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) > #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) > +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) > #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, > 10) > #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ > REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, > trans) > -- > 2.43.2
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d5ed4c7dfbc0..02cbbbfd8e25 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -30,6 +30,27 @@ #define KEY_LOAD_TRIES 5 #define HDCP2_LC_RETRY_CNT 3 +/* WA: 16022217614 */ +static void +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, + struct intel_hdcp *hdcp) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + /* Here we assume HDMI is in TMDS mode of operation */ + if (encoder->type != INTEL_OUTPUT_HDMI) + return; + + if (DISPLAY_VER(dev_priv) >= 14) { + if (IS_METEORLAKE(dev_priv)) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), + 0, HDCP_LINE_REKEY_DISABLE); + else + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), + 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + } +} + static int intel_conn_to_vcpi(struct intel_atomic_state *state, struct intel_connector *connector) { @@ -2005,6 +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state, connector->base.base.id, connector->base.name, hdcp->content_type); + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); + ret = hdcp2_authenticate_and_encrypt(state, connector); if (ret) { drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e22a82a5ddd7..31338d825e34 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3501,6 +3501,8 @@ [TRANSCODER_D] = _CHICKEN_TRANS_D)) #define _MTL_CHICKEN_TRANS_A 0x604e0 #define _MTL_CHICKEN_TRANS_B 0x614e0 +#define _MTL_CHICKEN_TRANS_C 0x624e0 +#define _MTL_CHICKEN_TRANS_D 0x634e0 #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ _MTL_CHICKEN_TRANS_A, \ _MTL_CHICKEN_TRANS_B) @@ -3519,6 +3521,7 @@ #define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) #define DISP_ARB_CTL _MMIO(0x45000) #define DISP_FBC_MEMORY_WAKE REG_BIT(31) @@ -4520,6 +4523,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI TMDS operation for DISPLAY_VER >= 14. --v2 -Wa to be mentioned in comments not in commit message [Jani] -Remove blankline [Jani] --v3 -No need to write what is being done in comments when code is self explanatory [Jani] --v4 -Add comment regarding need of this WA when in TMDS mode [Chaitanya] -Write in chicken register for MTL [CHaitanya] --v5 -Fix comment [Chaitanya] -Use correct set and clear value in intel_de_rmw [Chaitanya] Bspec: 49273 Bspec: 69964 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 27 insertions(+)