diff mbox series

[v2,03/21] drm/i915/dp: Move link train fallback to intel_dp_link_training.c

Message ID 20240520185822.3725844-4-imre.deak@intel.com (mailing list archive)
State New
Headers show
Series drm/i915/dp_mst: Enable link training fallback | expand

Commit Message

Imre Deak May 20, 2024, 6:58 p.m. UTC 
Move the functions used to reduce the link parameters during link
training to intel_dp_link_training.c .

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 76 +------------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  4 +-
 .../drm/i915/display/intel_dp_link_training.c | 73 ++++++++++++++++++
 3 files changed, 77 insertions(+), 76 deletions(-)

Comments

Ville Syrjälä May 22, 2024, 6:23 p.m. UTC | #1 
On Mon, May 20, 2024 at 09:58:01PM +0300, Imre Deak wrote:
> Move the functions used to reduce the link parameters during link
> training to intel_dp_link_training.c .
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 76 +------------------
>  drivers/gpu/drm/i915/display/intel_dp.h       |  4 +-
>  .../drm/i915/display/intel_dp_link_training.c | 73 ++++++++++++++++++
>  3 files changed, 77 insertions(+), 76 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ceedd3ef41946..81e620dd33bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -329,7 +329,7 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
>  				       intel_dp->num_common_rates, max_rate);
>  }
>  
> -static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
> +int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
>  {
>  	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
>  			index < 0 || index >= intel_dp->num_common_rates))
> @@ -604,7 +604,7 @@ static int intersect_rates(const int *source_rates, int source_len,
>  }
>  
>  /* return index of rate in rates array, or -1 if not found */
> -static int intel_dp_rate_index(const int *rates, int len, int rate)
> +int intel_dp_rate_index(const int *rates, int len, int rate)
>  {
>  	int i;
>  
> @@ -654,78 +654,6 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
>  	return true;
>  }
>  
> -static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
> -						     int link_rate,
> -						     u8 lane_count)
> -{
> -	/* FIXME figure out what we actually want here */
> -	const struct drm_display_mode *fixed_mode =
> -		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
> -	int mode_rate, max_rate;
> -
> -	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
> -	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
> -	if (mode_rate > max_rate)
> -		return false;
> -
> -	return true;
> -}
> -
> -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> -					    int link_rate, u8 lane_count)
> -{
> -	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> -	int index;
> -
> -	/*
> -	 * TODO: Enable fallback on MST links once MST link compute can handle
> -	 * the fallback params.
> -	 */
> -	if (intel_dp->is_mst) {
> -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> -		return -1;
> -	}
> -
> -	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> -		drm_dbg_kms(&i915->drm,
> -			    "Retrying Link training for eDP with max parameters\n");
> -		intel_dp->use_max_params = true;
> -		return 0;
> -	}
> -
> -	index = intel_dp_rate_index(intel_dp->common_rates,
> -				    intel_dp->num_common_rates,
> -				    link_rate);
> -	if (index > 0) {
> -		if (intel_dp_is_edp(intel_dp) &&
> -		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> -							      intel_dp_common_rate(intel_dp, index - 1),
> -							      lane_count)) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Retrying Link training for eDP with same parameters\n");
> -			return 0;
> -		}
> -		intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1);
> -		intel_dp->link.max_lane_count = lane_count;
> -	} else if (lane_count > 1) {
> -		if (intel_dp_is_edp(intel_dp) &&
> -		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> -							      intel_dp_max_common_rate(intel_dp),
> -							      lane_count >> 1)) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Retrying Link training for eDP with same parameters\n");
> -			return 0;
> -		}
> -		intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> -		intel_dp->link.max_lane_count = lane_count >> 1;
> -	} else {
> -		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> -		return -1;
> -	}
> -
> -	return 0;
> -}
> -
>  u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
>  {
>  	return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index aad2223df2a35..e7b47e7bcd98b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -55,8 +55,6 @@ void intel_dp_connector_sync_state(struct intel_connector *connector,
>  				   const struct intel_crtc_state *crtc_state);
>  void intel_dp_set_link_params(struct intel_dp *intel_dp,
>  			      int link_rate, int lane_count);
> -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> -					    int link_rate, u8 lane_count);
>  int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
>  			      struct drm_modeset_acquire_ctx *ctx,
>  			      u8 *pipe_mask);
> @@ -107,6 +105,8 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
>  int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
>  int intel_dp_max_common_rate(struct intel_dp *intel_dp);
>  int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
> +int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
> +int intel_dp_rate_index(const int *rates, int len, int rate);
>  void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
>  
>  void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 947575140059d..4db293f256896 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -25,6 +25,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dp_link_training.h"
> +#include "intel_panel.h"
>  
>  #define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
>  #define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
> @@ -1091,6 +1092,78 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp,
>  	return ret;
>  }
>  
> +static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
> +						     int link_rate,
> +						     u8 lane_count)
> +{
> +	/* FIXME figure out what we actually want here */
> +	const struct drm_display_mode *fixed_mode =
> +		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
> +	int mode_rate, max_rate;
> +
> +	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
> +	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
> +	if (mode_rate > max_rate)
> +		return false;
> +
> +	return true;
> +}
> +
> +static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> +						   int link_rate, u8 lane_count)
> +{
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +	int index;
> +
> +	/*
> +	 * TODO: Enable fallback on MST links once MST link compute can handle
> +	 * the fallback params.
> +	 */
> +	if (intel_dp->is_mst) {
> +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> +		return -1;
> +	}
> +
> +	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Retrying Link training for eDP with max parameters\n");
> +		intel_dp->use_max_params = true;
> +		return 0;
> +	}
> +
> +	index = intel_dp_rate_index(intel_dp->common_rates,
> +				    intel_dp->num_common_rates,
> +				    link_rate);
> +	if (index > 0) {
> +		if (intel_dp_is_edp(intel_dp) &&
> +		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> +							      intel_dp_common_rate(intel_dp, index - 1),
> +							      lane_count)) {
> +			drm_dbg_kms(&i915->drm,
> +				    "Retrying Link training for eDP with same parameters\n");
> +			return 0;
> +		}
> +		intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1);
> +		intel_dp->link.max_lane_count = lane_count;
> +	} else if (lane_count > 1) {
> +		if (intel_dp_is_edp(intel_dp) &&
> +		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
> +							      intel_dp_max_common_rate(intel_dp),
> +							      lane_count >> 1)) {
> +			drm_dbg_kms(&i915->drm,
> +				    "Retrying Link training for eDP with same parameters\n");
> +			return 0;
> +		}
> +		intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
> +		intel_dp->link.max_lane_count = lane_count >> 1;
> +	} else {
> +		drm_err(&i915->drm, "Link Training Unsuccessful\n");
> +		return -1;
> +	}
> +
> +	return 0;
> +}
> +
>  static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
>  						     const struct intel_crtc_state *crtc_state)
>  {
> -- 
> 2.43.3
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ceedd3ef41946..81e620dd33bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -329,7 +329,7 @@  static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 				       intel_dp->num_common_rates, max_rate);
 }
 
-static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
+int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 {
 	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 			index < 0 || index >= intel_dp->num_common_rates))
@@ -604,7 +604,7 @@  static int intersect_rates(const int *source_rates, int source_len,
 }
 
 /* return index of rate in rates array, or -1 if not found */
-static int intel_dp_rate_index(const int *rates, int len, int rate)
+int intel_dp_rate_index(const int *rates, int len, int rate)
 {
 	int i;
 
@@ -654,78 +654,6 @@  static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 	return true;
 }
 
-static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
-						     int link_rate,
-						     u8 lane_count)
-{
-	/* FIXME figure out what we actually want here */
-	const struct drm_display_mode *fixed_mode =
-		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
-	int mode_rate, max_rate;
-
-	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
-	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
-	if (mode_rate > max_rate)
-		return false;
-
-	return true;
-}
-
-int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
-					    int link_rate, u8 lane_count)
-{
-	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
-	int index;
-
-	/*
-	 * TODO: Enable fallback on MST links once MST link compute can handle
-	 * the fallback params.
-	 */
-	if (intel_dp->is_mst) {
-		drm_err(&i915->drm, "Link Training Unsuccessful\n");
-		return -1;
-	}
-
-	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
-		drm_dbg_kms(&i915->drm,
-			    "Retrying Link training for eDP with max parameters\n");
-		intel_dp->use_max_params = true;
-		return 0;
-	}
-
-	index = intel_dp_rate_index(intel_dp->common_rates,
-				    intel_dp->num_common_rates,
-				    link_rate);
-	if (index > 0) {
-		if (intel_dp_is_edp(intel_dp) &&
-		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-							      intel_dp_common_rate(intel_dp, index - 1),
-							      lane_count)) {
-			drm_dbg_kms(&i915->drm,
-				    "Retrying Link training for eDP with same parameters\n");
-			return 0;
-		}
-		intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1);
-		intel_dp->link.max_lane_count = lane_count;
-	} else if (lane_count > 1) {
-		if (intel_dp_is_edp(intel_dp) &&
-		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
-							      intel_dp_max_common_rate(intel_dp),
-							      lane_count >> 1)) {
-			drm_dbg_kms(&i915->drm,
-				    "Retrying Link training for eDP with same parameters\n");
-			return 0;
-		}
-		intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
-		intel_dp->link.max_lane_count = lane_count >> 1;
-	} else {
-		drm_err(&i915->drm, "Link Training Unsuccessful\n");
-		return -1;
-	}
-
-	return 0;
-}
-
 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 {
 	return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index aad2223df2a35..e7b47e7bcd98b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -55,8 +55,6 @@  void intel_dp_connector_sync_state(struct intel_connector *connector,
 				   const struct intel_crtc_state *crtc_state);
 void intel_dp_set_link_params(struct intel_dp *intel_dp,
 			      int link_rate, int lane_count);
-int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
-					    int link_rate, u8 lane_count);
 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
 			      struct drm_modeset_acquire_ctx *ctx,
 			      u8 *pipe_mask);
@@ -107,6 +105,8 @@  int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
 int intel_dp_max_common_rate(struct intel_dp *intel_dp);
 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp);
+int intel_dp_common_rate(struct intel_dp *intel_dp, int index);
+int intel_dp_rate_index(const int *rates, int len, int rate);
 void intel_dp_update_sink_caps(struct intel_dp *intel_dp);
 
 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 947575140059d..4db293f256896 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -25,6 +25,7 @@ 
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dp_link_training.h"
+#include "intel_panel.h"
 
 #define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
 #define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
@@ -1091,6 +1092,78 @@  intel_dp_link_train_phy(struct intel_dp *intel_dp,
 	return ret;
 }
 
+static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
+						     int link_rate,
+						     u8 lane_count)
+{
+	/* FIXME figure out what we actually want here */
+	const struct drm_display_mode *fixed_mode =
+		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
+	int mode_rate, max_rate;
+
+	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
+	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
+	if (mode_rate > max_rate)
+		return false;
+
+	return true;
+}
+
+static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
+						   int link_rate, u8 lane_count)
+{
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+	int index;
+
+	/*
+	 * TODO: Enable fallback on MST links once MST link compute can handle
+	 * the fallback params.
+	 */
+	if (intel_dp->is_mst) {
+		drm_err(&i915->drm, "Link Training Unsuccessful\n");
+		return -1;
+	}
+
+	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
+		drm_dbg_kms(&i915->drm,
+			    "Retrying Link training for eDP with max parameters\n");
+		intel_dp->use_max_params = true;
+		return 0;
+	}
+
+	index = intel_dp_rate_index(intel_dp->common_rates,
+				    intel_dp->num_common_rates,
+				    link_rate);
+	if (index > 0) {
+		if (intel_dp_is_edp(intel_dp) &&
+		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
+							      intel_dp_common_rate(intel_dp, index - 1),
+							      lane_count)) {
+			drm_dbg_kms(&i915->drm,
+				    "Retrying Link training for eDP with same parameters\n");
+			return 0;
+		}
+		intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1);
+		intel_dp->link.max_lane_count = lane_count;
+	} else if (lane_count > 1) {
+		if (intel_dp_is_edp(intel_dp) &&
+		    !intel_dp_can_link_train_fallback_for_edp(intel_dp,
+							      intel_dp_max_common_rate(intel_dp),
+							      lane_count >> 1)) {
+			drm_dbg_kms(&i915->drm,
+				    "Retrying Link training for eDP with same parameters\n");
+			return 0;
+		}
+		intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
+		intel_dp->link.max_lane_count = lane_count >> 1;
+	} else {
+		drm_err(&i915->drm, "Link Training Unsuccessful\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
 						     const struct intel_crtc_state *crtc_state)
 {