diff mbox series

[v9,1/8] drm/i915: Define and compute Transcoder CMRR registers

Message ID 20240524102432.2499104-2-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
State New
Headers show
Series Implement CMRR Support | expand

Commit Message

Golani, Mitulkumar Ajitkumar May 24, 2024, 10:24 a.m. UTC 
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.

--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]

--v3:
- Removing RFC tag.

--v4:
- Update place holder for CMRR register definition. (Jani)

--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 23 ++++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |  6 +++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_vrr_reg.h          | 21 +++++++++++++++++
 4 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_vrr_reg.h

Comments

Jani Nikula May 27, 2024, 10:50 a.m. UTC | #1 
On Fri, 24 May 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h b/drivers/gpu/drm/i915/intel_vrr_reg.h
> new file mode 100644
> index 000000000000..e1273b4e1b9b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_vrr_reg.h

We'll want to call this intel_vrr_regs.h, not _reg.h.

$ find drivers/gpu/drm/i915/ -name "*_reg*.h" | grep -o "regs*.h" | sort | uniq -c
      4 reg.h
     38 regs.h

> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_VRR_REG_H__
> +#define __INTEL_VRR_REG_H__
> +
> +#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
> +
> +#define	_TRANS_CMRR_M_LO_A                  0x604F0
> +#define	_TRANS_CMRR_M_HI_A		            0x604F4
> +#define	_TRANS_CMRR_N_LO_A		            0x604F8
> +#define	_TRANS_CMRR_N_HI_A		            0x604FC
> +#define	TRANS_CMRR_M_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
> +#define	TRANS_CMRR_M_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
> +#define	TRANS_CMRR_N_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
> +#define	TRANS_CMRR_N_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)

Please read the big comment near the top of i915_reg.h about ordering
and indenting and all that stuff.

See what Ville's doing here [1] to clean up.


BR,
Jani.

[1] https://lore.kernel.org/r/20240516135622.3498-3-ville.syrjala@linux.intel.com
Jani Nikula May 27, 2024, 10:52 a.m. UTC | #2 
On Mon, 27 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 24 May 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h b/drivers/gpu/drm/i915/intel_vrr_reg.h
>> new file mode 100644
>> index 000000000000..e1273b4e1b9b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_vrr_reg.h
>
> We'll want to call this intel_vrr_regs.h, not _reg.h.
>
> $ find drivers/gpu/drm/i915/ -name "*_reg*.h" | grep -o "regs*.h" | sort | uniq -c
>       4 reg.h
>      38 regs.h
>
>> @@ -0,0 +1,21 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2024 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_VRR_REG_H__
>> +#define __INTEL_VRR_REG_H__
>> +
>> +#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
>> +
>> +#define	_TRANS_CMRR_M_LO_A                  0x604F0
>> +#define	_TRANS_CMRR_M_HI_A		            0x604F4
>> +#define	_TRANS_CMRR_N_LO_A		            0x604F8
>> +#define	_TRANS_CMRR_N_HI_A		            0x604FC
>> +#define	TRANS_CMRR_M_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
>> +#define	TRANS_CMRR_M_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
>> +#define	TRANS_CMRR_N_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
>> +#define	TRANS_CMRR_N_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
>
> Please read the big comment near the top of i915_reg.h about ordering
> and indenting and all that stuff.
>
> See what Ville's doing here [1] to clean up.
>
>
> BR,
> Jani.
>
> [1] https://lore.kernel.org/r/20240516135622.3498-3-ville.syrjala@linux.intel.com

PS. This also depends on intel_display_reg_defs.h.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e8e2fd52cf6..803360fcb0cc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1004,6 +1004,13 @@  static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 }
 
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+				const struct intel_crtc_state *new_crtc_state)
+{
+	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 			 const struct intel_crtc_state *new_crtc_state)
 {
@@ -5054,6 +5061,16 @@  intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_LLI(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+				     "(expected %lli, found %lli)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_BOOL(name) do { \
 	if (current_config->name != pipe_config->name) { \
 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5418,10 +5435,13 @@  intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.guardband);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 	}
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
 #undef PIPE_CONF_CHECK_BOOL
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
@@ -6810,7 +6830,8 @@  static void intel_pre_update_crtc(struct intel_atomic_state *state,
 		    intel_crtc_needs_fastset(new_crtc_state))
 			icl_set_pipe_chicken(new_crtc_state);
 
-		if (vrr_params_changed(old_crtc_state, new_crtc_state))
+		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+		    cmrr_params_changed(old_crtc_state, new_crtc_state))
 			intel_vrr_set_transcoder_timings(new_crtc_state);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9678c2b157f6..ee0323422c7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1401,6 +1401,12 @@  struct intel_crtc_state {
 		u32 vsync_end, vsync_start;
 	} vrr;
 
+	/* Content Match Refresh Rate state */
+	struct {
+		bool enable;
+		u64 cmrr_n, cmrr_m;
+	} cmrr;
+
 	/* Stream Splitter for eDP MSO */
 	struct {
 		bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5f3657aa8313..b96a8b2e7083 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@ 
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_vrr_reg.h"
 #include "intel_dp.h"
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
@@ -218,6 +219,19 @@  void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+			       VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+		intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+		intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+	}
+
 	intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
 		       crtc_state->vrr.vmin - 1);
 	intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
@@ -306,6 +320,15 @@  void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
 
+	if (crtc_state->cmrr.enable) {
+		crtc_state->cmrr.cmrr_n =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+					     TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
+		crtc_state->cmrr.cmrr_m =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+					     TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
+	}
+
 	if (DISPLAY_VER(dev_priv) >= 13)
 		crtc_state->vrr.guardband =
 			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h b/drivers/gpu/drm/i915/intel_vrr_reg.h
new file mode 100644
index 000000000000..e1273b4e1b9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vrr_reg.h
@@ -0,0 +1,21 @@ 
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_VRR_REG_H__
+#define __INTEL_VRR_REG_H__
+
+#define   VRR_CTL_CMRR_ENABLE			REG_BIT(27)
+
+#define	_TRANS_CMRR_M_LO_A                  0x604F0
+#define	_TRANS_CMRR_M_HI_A		            0x604F4
+#define	_TRANS_CMRR_N_LO_A		            0x604F8
+#define	_TRANS_CMRR_N_HI_A		            0x604FC
+#define	TRANS_CMRR_M_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
+#define	TRANS_CMRR_M_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
+#define	TRANS_CMRR_N_LO(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
+#define	TRANS_CMRR_N_HI(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
+
+#endif /* __INTEL_VRR_REGS__ */
+