diff mbox series

[v6,09/26] drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid

Message ID 20240605102553.187309-10-jouni.hogander@intel.com (mailing list archive)
State New
Headers show
Series Panel Replay eDP support | expand

Commit Message

Jouni Högander June 5, 2024, 10:25 a.m. UTC
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

Comments

Manna, Animesh June 6, 2024, 3:01 p.m. UTC | #1
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Wednesday, June 5, 2024 3:56 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Kahola, Mika
> <mika.kahola@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>
> Subject: [PATCH v6 09/26] drm/i915/psr: Add Panel Replay support to
> intel_psr2_config_et_valid
> 
> Early Transport is possible and in our HW mandatory on eDP Panel Replay.
> Add parameter to intel_psr2_config_et_valid to differentiate validity check
> for Panel Replay.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a3ad4488fcee..7bdae0d0ea45 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -664,16 +664,17 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
>  		       aux_ctl);
>  }
> 
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool
> +panel_replay)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> 
> -	if (DISPLAY_VER(i915) >= 20 &&
> -	    intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> -	    !(intel_dp->psr.debug &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
> -		return true;
> +	if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
> +	    intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
> +		return false;
> 
> -	return false;
> +	return panel_replay ?
> +		intel_dp->pr_dpcd &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> +		intel_dp->psr_dpcd[0] !=
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
>  }
> 
>  static void _panel_replay_enable_sink(struct intel_dp *intel_dp, @@ -
> 1351,7 +1352,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> 
>  	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
> 
> -	if (psr2_su_region_et_valid(intel_dp))
> +	if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay))
>  		crtc_state->enable_psr2_su_region_et = true;
> 
>  	return true;
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a3ad4488fcee..7bdae0d0ea45 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -664,16 +664,17 @@  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		       aux_ctl);
 }
 
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
-	if (DISPLAY_VER(i915) >= 20 &&
-	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
-	    !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
-		return true;
+	if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
+	    intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
+		return false;
 
-	return false;
+	return panel_replay ?
+		intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
+		intel_dp->psr_dpcd[0] != DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
 }
 
 static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
@@ -1351,7 +1352,7 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 
-	if (psr2_su_region_et_valid(intel_dp))
+	if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay))
 		crtc_state->enable_psr2_su_region_et = true;
 
 	return true;