@@ -692,6 +692,7 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
+ u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION;
if (crtc_state->has_sel_update)
val |= DP_PANEL_REPLAY_SU_ENABLE;
@@ -699,7 +700,14 @@ static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_su_region_et)
val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET;
+ if (crtc_state->req_psr2_sdp_prior_scanline)
+ panel_replay_config2 |=
+ DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE;
+
drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val);
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2,
+ panel_replay_config2);
}
static void _psr_enable_sink(struct intel_dp *intel_dp,
@@ -727,15 +735,31 @@ static void _psr_enable_sink(struct intel_dp *intel_dp,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);
}
+static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ u8 val;
+
+ /*
+ * eDP Panel Replay uses always ALPM
+ * PSR2 uses ALPM but PSR1 doesn't
+ */
+ if (!intel_dp_is_edp(intel_dp) || (!crtc_state->has_panel_replay &&
+ !crtc_state->has_sel_update))
+ return;
+
+ val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
+
+ if (crtc_state->has_panel_replay)
+ val |= DP_ALPM_MODE_AUX_LESS;
+
+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
+}
+
void intel_psr_enable_sink(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
- /* Enable ALPM at sink for psr2 */
- if (!crtc_state->has_panel_replay && crtc_state->has_sel_update)
- drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_RECEIVER_ALPM_CONFIG,
- DP_ALPM_ENABLE |
- DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
+ intel_psr_enable_sink_alpm(intel_dp, crtc_state);
crtc_state->has_panel_replay ?
_panel_replay_enable_sink(intel_dp, crtc_state) :
eDP1.5 allows Panel Replay on eDP as well. Take this into account when enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register accordingly. v3: - set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2 - PANEL_REPLAY_CONFIG2 is available in DP2.1 as well v2: do not configure ALPM for DP2.0 Panel Replay Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 36 ++++++++++++++++++++---- 1 file changed, 30 insertions(+), 6 deletions(-)