| Message ID | 20240605170111.494784-2-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implement CMRR Support | expand |
On 6/5/2024 10:31 PM, Mitul Golani wrote: > Update the indentation for the VRR register definition and > its bits, and fix checkpatch issues to ensure smooth movement > of registers and bits. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> LGTM Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0569a23b83b2..6b39211b5469 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1152,7 +1152,7 @@ > #define _TRANS_VRR_CTL_B 0x61420 > #define _TRANS_VRR_CTL_C 0x62420 > #define _TRANS_VRR_CTL_D 0x63420 > -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) > +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) > #define VRR_CTL_VRR_ENABLE REG_BIT(31) > #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) > #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) > @@ -1160,7 +1160,8 @@ > #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) > #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) > #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) > -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) > +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ > + (x)) > > #define _TRANS_VRR_VMAX_A 0x60424 > #define _TRANS_VRR_VMAX_B 0x61424 > @@ -1190,7 +1191,7 @@ > #define _TRANS_VRR_STATUS_B 0x6142C > #define _TRANS_VRR_STATUS_C 0x6242C > #define _TRANS_VRR_STATUS_D 0x6342C > -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) > +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) > #define VRR_STATUS_VMAX_REACHED REG_BIT(31) > #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) > #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > @@ -1241,7 +1242,7 @@ > #define TRANS_PUSH_SEND REG_BIT(30) > > #define _TRANS_VRR_VSYNC_A 0x60078 > -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) > +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) > #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) > #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) > #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
On 6/7/2024 8:59 AM, Nautiyal, Ankit K wrote: > > On 6/5/2024 10:31 PM, Mitul Golani wrote: >> Update the indentation for the VRR register definition and >> its bits, and fix checkpatch issues to ensure smooth movement >> of registers and bits. >> >> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > > LGTM > > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Having look at the next patch, I fee there are still few things that can be fixed in VRR regs since we are moving these into a new file. IMHO, it would be great if we can make the changes so that the new file adheres to the formatting mentioned in i915_reg.h Regards, Ankit > > >> --- >> drivers/gpu/drm/i915/i915_reg.h | 9 +++++---- >> 1 file changed, 5 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h >> index 0569a23b83b2..6b39211b5469 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1152,7 +1152,7 @@ >> #define _TRANS_VRR_CTL_B 0x61420 >> #define _TRANS_VRR_CTL_C 0x62420 >> #define _TRANS_VRR_CTL_D 0x63420 >> -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, >> _TRANS_VRR_CTL_A) >> +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, >> _TRANS_VRR_CTL_A) >> #define VRR_CTL_VRR_ENABLE REG_BIT(31) >> #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) >> #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) >> @@ -1160,7 +1160,8 @@ >> #define VRR_CTL_PIPELINE_FULL(x) >> REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) >> #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) >> #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) >> -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) >> REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) >> +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) >> REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ >> + (x)) >> #define _TRANS_VRR_VMAX_A 0x60424 >> #define _TRANS_VRR_VMAX_B 0x61424 >> @@ -1190,7 +1191,7 @@ >> #define _TRANS_VRR_STATUS_B 0x6142C >> #define _TRANS_VRR_STATUS_C 0x6242C >> #define _TRANS_VRR_STATUS_D 0x6342C >> -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, >> trans, _TRANS_VRR_STATUS_A) >> +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, >> trans, _TRANS_VRR_STATUS_A) >> #define VRR_STATUS_VMAX_REACHED REG_BIT(31) >> #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) >> #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) >> @@ -1241,7 +1242,7 @@ >> #define TRANS_PUSH_SEND REG_BIT(30) >> #define _TRANS_VRR_VSYNC_A 0x60078 >> -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, >> trans, _TRANS_VRR_VSYNC_A) >> +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, >> trans, _TRANS_VRR_VSYNC_A) >> #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) >> #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, >> (vsync_end)) >> #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0569a23b83b2..6b39211b5469 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1152,7 +1152,7 @@ #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) @@ -1160,7 +1160,8 @@ #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \ + (x)) #define _TRANS_VRR_VMAX_A 0x60424 #define _TRANS_VRR_VMAX_B 0x61424 @@ -1190,7 +1191,7 @@ #define _TRANS_VRR_STATUS_B 0x6142C #define _TRANS_VRR_STATUS_C 0x6242C #define _TRANS_VRR_STATUS_D 0x6342C -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) #define VRR_STATUS_VMAX_REACHED REG_BIT(31) #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) @@ -1241,7 +1242,7 @@ #define TRANS_PUSH_SEND REG_BIT(30) #define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)