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Fri, 28 Jun 2024 09:45:34 -0700 (PDT) From: Juha-Pekka Heikkila To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Juha-Pekka Heikkila Subject: [PATCH 1/1] drm/i915/display: On Xe2 platform always require ccs alignment on tile4 Date: Fri, 28 Jun 2024 19:49:00 +0300 Message-ID: <20240628164900.2737389-2-juhapekka.heikkila@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240628164900.2737389-1-juhapekka.heikkila@gmail.com> References: <20240628164900.2737389-1-juhapekka.heikkila@gmail.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Xe2 platform with tile4 decompression is enabled unconditionally hence consider tile4 as ccs modifier Signed-off-by: Juha-Pekka Heikkila --- drivers/gpu/drm/i915/display/intel_fb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index f23547a88b1f..c36d5a9dc5ac 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1733,7 +1733,8 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) } tile_width = intel_tile_width_bytes(fb, color_plane); - if (intel_fb_is_ccs_modifier(fb->modifier)) { + if (intel_fb_is_ccs_modifier(fb->modifier) || + (GRAPHICS_VER(dev_priv) >= 20 && fb->modifier == I915_FORMAT_MOD_4_TILED)) { /* * On TGL the surface stride must be 4 tile aligned, mapped by * one 64 byte cacheline on the CCS AUX surface.