diff mbox series

[04/10] drm/i915/vrr: Compute vrr vsync if platforms support it

Message ID 20240709032651.1824185-5-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Ankit Nautiyal July 9, 2024, 3:26 a.m. UTC
Previously, TRANS_VRR_VSYNC was exclusively used for panels with
adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
rates using the VRR Timing generator, we now need to program
TRANS_VRR_VSYNC regardless of adaptive sync SDP support. Therefore, let's
remove the adaptive sync SDP check and program TRANS_VRR_VSYNC for
platforms where VRR timing generator is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Mitul Golani July 16, 2024, 4:06 a.m. UTC | #1
> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Tuesday, July 9, 2024 8:57 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: jani.nikula@linux.intel.com; ville.syrjala@linux.intel.com; Golani,
> Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
> Subject: [PATCH 04/10] drm/i915/vrr: Compute vrr vsync if platforms support it
> 
> Previously, TRANS_VRR_VSYNC was exclusively used for panels with adaptive-
> sync SDP support in VRR scenarios. However, to drive fixed refresh rates using
> the VRR Timing generator, we now need to program TRANS_VRR_VSYNC
> regardless of adaptive sync SDP support. Therefore, let's remove the adaptive

In this case still do we need to add source check for HAS_AS_SDP(i915) ?

Regards,
Mitul

> sync SDP check and program TRANS_VRR_VSYNC for platforms where VRR
> timing generator is used.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 24568dae717a..43b772f91556 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -233,8 +233,7 @@ intel_vrr_compute_config(struct intel_crtc_state
> *crtc_state,
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  	}
> 
> -	if (intel_dp_as_sdp_supported(intel_dp) &&
> -	    crtc_state->vrr.enable) {
> +	if (HAS_AS_SDP(i915) && crtc_state->vrr.enable) {
>  		crtc_state->vrr.vsync_start =
>  			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>  			 crtc_state->hw.adjusted_mode.vsync_start);
> --
> 2.40.1
Ankit Nautiyal July 16, 2024, 6:24 a.m. UTC | #2
On 7/16/2024 9:36 AM, Golani, Mitulkumar Ajitkumar wrote:
>
>> -----Original Message-----
>> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
>> Sent: Tuesday, July 9, 2024 8:57 AM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: jani.nikula@linux.intel.com; ville.syrjala@linux.intel.com; Golani,
>> Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>
>> Subject: [PATCH 04/10] drm/i915/vrr: Compute vrr vsync if platforms support it
>>
>> Previously, TRANS_VRR_VSYNC was exclusively used for panels with adaptive-
>> sync SDP support in VRR scenarios. However, to drive fixed refresh rates using
>> the VRR Timing generator, we now need to program TRANS_VRR_VSYNC
>> regardless of adaptive sync SDP support. Therefore, let's remove the adaptive
> In this case still do we need to add source check for HAS_AS_SDP(i915) ?

We still need to ensure that we do not write this for platforms where it 
is not supported.

I have added the check, as this was introduced for AS SDP originally for 
DISPLAY >= 13

Regards,

Ankit

>
> Regards,
> Mitul
>
>> sync SDP check and program TRANS_VRR_VSYNC for platforms where VRR
>> timing generator is used.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 24568dae717a..43b772f91556 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -233,8 +233,7 @@ intel_vrr_compute_config(struct intel_crtc_state
>> *crtc_state,
>>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   	}
>>
>> -	if (intel_dp_as_sdp_supported(intel_dp) &&
>> -	    crtc_state->vrr.enable) {
>> +	if (HAS_AS_SDP(i915) && crtc_state->vrr.enable) {
>>   		crtc_state->vrr.vsync_start =
>>   			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>>   			 crtc_state->hw.adjusted_mode.vsync_start);
>> --
>> 2.40.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 24568dae717a..43b772f91556 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -233,8 +233,7 @@  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 	}
 
-	if (intel_dp_as_sdp_supported(intel_dp) &&
-	    crtc_state->vrr.enable) {
+	if (HAS_AS_SDP(i915) && crtc_state->vrr.enable) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.vsync_start);