| Message ID | 20240723042802.3618046-1-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Clear VSC SDP during post ddi disable routine | expand |
On 7/23/2024 9:58 AM, Suraj Kandpal wrote: > Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable > routine i.e with the variable of enable as false. This is to avoid > an infoframes.enable mismatch issue which is caused when pipe is > connected to eDp which has psr then connected to DPMST. In this case > eDp's post ddi disable routine does not clear infoframes.enable VSC > for the given pipe and DPMST does not recompute VSC SDP and write > infoframes.enable which causes a mismatch. > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> LGTM Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 1e43e32e0519..8b60d7f34ab8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4370,7 +4370,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, > val &= ~VDIP_ENABLE_PPS; > > /* When PSR is enabled, this routine doesn't disable VSC DIP */ > - if (!crtc_state->has_psr) > + if (!enable || !crtc_state->has_psr) > val &= ~VIDEO_DIP_ENABLE_VSC_HSW; > > intel_de_write(dev_priv, reg, val);
On Wed, 24 Jul 2024, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote: > On 7/23/2024 9:58 AM, Suraj Kandpal wrote: >> Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable >> routine i.e with the variable of enable as false. This is to avoid >> an infoframes.enable mismatch issue which is caused when pipe is >> connected to eDp which has psr then connected to DPMST. In this case >> eDp's post ddi disable routine does not clear infoframes.enable VSC >> for the given pipe and DPMST does not recompute VSC SDP and write >> infoframes.enable which causes a mismatch. >> >> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > LGTM > > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > >> --- >> drivers/gpu/drm/i915/display/intel_dp.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index 1e43e32e0519..8b60d7f34ab8 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -4370,7 +4370,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, >> val &= ~VDIP_ENABLE_PPS; >> >> /* When PSR is enabled, this routine doesn't disable VSC DIP */ >> - if (!crtc_state->has_psr) >> + if (!enable || !crtc_state->has_psr) The comment no longer matches the code with this. BR, Jani. >> val &= ~VIDEO_DIP_ENABLE_VSC_HSW; >> >> intel_de_write(dev_priv, reg, val);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1e43e32e0519..8b60d7f34ab8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4370,7 +4370,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, val &= ~VDIP_ENABLE_PPS; /* When PSR is enabled, this routine doesn't disable VSC DIP */ - if (!crtc_state->has_psr) + if (!enable || !crtc_state->has_psr) val &= ~VIDEO_DIP_ENABLE_VSC_HSW; intel_de_write(dev_priv, reg, val);
Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable routine i.e with the variable of enable as false. This is to avoid an infoframes.enable mismatch issue which is caused when pipe is connected to eDp which has psr then connected to DPMST. In this case eDp's post ddi disable routine does not clear infoframes.enable VSC for the given pipe and DPMST does not recompute VSC SDP and write infoframes.enable which causes a mismatch. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)