diff mbox series

drm/i915/display: Workaround for odd panning for planar yuv

Message ID 20240724113026.940791-1-nemesa.garg@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: Workaround for odd panning for planar yuv | expand

Commit Message

Nemesa Garg July 24, 2024, 11:30 a.m. UTC
Underrun/corruption issue is seen for NV12 format
for odd panning on LNL due to hardware bug.
Disable the format.

HSD: 16024459452

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e979786aa5cf..f927e6a0b28b 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1029,6 +1029,14 @@  int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		 * This allows NV12 and P0xx formats to have odd size and/or odd
 		 * source coordinates on DISPLAY_VER(i915) >= 20
 		 */
+
+		/*
+		 * Wa_16023981245 for display version 20.
+		 * Disable odd pan for NV12 format.
+		 */
+		if (DISPLAY_VER(i915) == 20 && fb->format->format == DRM_FORMAT_NV12)
+			return 0;
+
 		hsub = 1;
 		vsub = 1;
 	} else {