diff mbox series

[v2] drm/i915/bmg: Read display register timeout

Message ID 20240807040307.1246114-1-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2] drm/i915/bmg: Read display register timeout | expand

Commit Message

Golani, Mitulkumar Ajitkumar Aug. 7, 2024, 4:03 a.m. UTC
Log the address of the register that caused the timeout
interrupt by reading RMTIMEOUTREG_CAPTURE

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c | 7 ++++++-
 drivers/gpu/drm/i915/i915_reg.h                  | 2 ++
 2 files changed, 8 insertions(+), 1 deletion(-)

Comments

Suraj Kandpal Aug. 7, 2024, 8:44 a.m. UTC | #1
> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Sent: Wednesday, August 7, 2024 9:33 AM
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Kandpal,
> Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH v2] drm/i915/bmg: Read display register timeout
> 
> Log the address of the register that caused the timeout interrupt by reading
> RMTIMEOUTREG_CAPTURE
> 

Mention the changes that were added compared to the previous revisions

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 7 ++++++-
>  drivers/gpu/drm/i915/i915_reg.h                  | 2 ++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 5219ba295c74..5ebc1fd10a92 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -905,6 +905,11 @@ gen8_de_misc_irq_handler(struct
> drm_i915_private *dev_priv, u32 iir)
> 
>  			intel_pmdemand_irq_handler(dev_priv);
>  			found = true;
> +		} else if (iir & GEN8_DE_RM_TIMEOUT) {

This here shouldn't be in else if but should be its own if condition.
Also since this GEN8_DE_RM_TIMEOUT bit is being introduced here and will
Only be used from display 14 onwards lets use the XeLpd naming convention
Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> +			u32 val = intel_uncore_read(&dev_priv->uncore,
> +
> RM_TIMEOUT_REG_CAPTURE);
> +			drm_warn(&dev_priv->drm, "Register Access
> Timeout = 0x%x\n", val);
> +			found = true;
>  		}
>  	} else if (iir & GEN8_DE_MISC_GSE) {
>  		intel_opregion_asle_intr(dev_priv);
> @@ -1710,7 +1715,7 @@ void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> -				  XELPDP_PMDEMAND_RSP;
> +				  XELPDP_PMDEMAND_RSP |
> GEN8_DE_RM_TIMEOUT;
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		enum port port;
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 0e3d79227e3c..54df05046ad8
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2396,6 +2396,7 @@
> 
>  /* Display Internal Timeout Register */
>  #define RM_TIMEOUT		_MMIO(0x42060)
> +#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
>  #define  MMIO_TIMEOUT_US(us)	((us) << 0)
> 
>  /* interrupts */
> @@ -2574,6 +2575,7 @@
>  #define GEN8_DE_MISC_IMR _MMIO(0x44464)  #define GEN8_DE_MISC_IIR
> _MMIO(0x44468)  #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> +#define  GEN8_DE_RM_TIMEOUT		REG_BIT(29)
>  #define  XELPDP_PMDEMAND_RSPTOUT_ERR	REG_BIT(27)
>  #define  GEN8_DE_MISC_GSE		REG_BIT(27)
>  #define  GEN8_DE_EDP_PSR		REG_BIT(19)
> --
> 2.45.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 5219ba295c74..5ebc1fd10a92 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -905,6 +905,11 @@  gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 
 			intel_pmdemand_irq_handler(dev_priv);
 			found = true;
+		} else if (iir & GEN8_DE_RM_TIMEOUT) {
+			u32 val = intel_uncore_read(&dev_priv->uncore,
+						    RM_TIMEOUT_REG_CAPTURE);
+			drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val);
+			found = true;
 		}
 	} else if (iir & GEN8_DE_MISC_GSE) {
 		intel_opregion_asle_intr(dev_priv);
@@ -1710,7 +1715,7 @@  void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
-				  XELPDP_PMDEMAND_RSP;
+				  XELPDP_PMDEMAND_RSP | GEN8_DE_RM_TIMEOUT;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
 		enum port port;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e3d79227e3c..54df05046ad8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2396,6 +2396,7 @@ 
 
 /* Display Internal Timeout Register */
 #define RM_TIMEOUT		_MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
 
 /* interrupts */
@@ -2574,6 +2575,7 @@ 
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
+#define  GEN8_DE_RM_TIMEOUT		REG_BIT(29)
 #define  XELPDP_PMDEMAND_RSPTOUT_ERR	REG_BIT(27)
 #define  GEN8_DE_MISC_GSE		REG_BIT(27)
 #define  GEN8_DE_EDP_PSR		REG_BIT(19)