| Message ID | 20240822061448.4085693-1-chaitanya.kumar.borah@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates | expand |
On Thu, Aug 22, 2024 at 11:44:48AM +0530, Chaitanya Kumar Borah wrote: > In case of UHBR rates, we do not need to explicitly enable FEC by writing > to DP_TP_CTL register. > For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of > setting fec_enable to false. However, it gets overwritten in > intel_dp_dsc_compute_config(). This change keeps fec_enable false across > MST and SST use-cases for UHBR rates. > > While at it, add a comment explaining why we don't enable FEC in eDP v1.5. > > v2: Correct logic to cater to SST use-cases (Jani) > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 49a37b996530..de30eaacd9b4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2298,9 +2298,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > &pipe_config->hw.adjusted_mode; > int ret; > > + /* > + * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. > + * Since, FEC is a bandwidth overhead, continue to not enable it for > + * eDP. Until, there is a good reason to do so. > + */ > pipe_config->fec_enable = pipe_config->fec_enable || > (!intel_dp_is_edp(intel_dp) && > - intel_dp_supports_fec(intel_dp, connector, pipe_config)); > + intel_dp_supports_fec(intel_dp, connector, pipe_config) && > + !intel_dp_is_uhbr(pipe_config)); I think this should be only computed by the DP encoder specific handler (in intel_dp_compute_link_config()) instead of recomputing here for the DP MST case as well. Also intel_dp_supports_dsc() just happens to work now, since it doesn't check for this flag on MST, so that may need to be updated. Both of these can be done as a follow up, so for this patch: Reviewed-by: Imre Deak <imre.deak@intel.com> > > if (!intel_dp_supports_dsc(connector, pipe_config)) > return -EINVAL; > -- > 2.25.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 49a37b996530..de30eaacd9b4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2298,9 +2298,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, &pipe_config->hw.adjusted_mode; int ret; + /* + * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional. + * Since, FEC is a bandwidth overhead, continue to not enable it for + * eDP. Until, there is a good reason to do so. + */ pipe_config->fec_enable = pipe_config->fec_enable || (!intel_dp_is_edp(intel_dp) && - intel_dp_supports_fec(intel_dp, connector, pipe_config)); + intel_dp_supports_fec(intel_dp, connector, pipe_config) && + !intel_dp_is_uhbr(pipe_config)); if (!intel_dp_supports_dsc(connector, pipe_config)) return -EINVAL;
In case of UHBR rates, we do not need to explicitly enable FEC by writing to DP_TP_CTL register. For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of setting fec_enable to false. However, it gets overwritten in intel_dp_dsc_compute_config(). This change keeps fec_enable false across MST and SST use-cases for UHBR rates. While at it, add a comment explaining why we don't enable FEC in eDP v1.5. v2: Correct logic to cater to SST use-cases (Jani) Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)