diff mbox series

[PATCHv2] drm/i915/display: BMG supports UHBR13.5

Message ID 20240827081205.136569-1-arun.r.murthy@intel.com (mailing list archive)
State New
Headers show
Series [PATCHv2] drm/i915/display: BMG supports UHBR13.5 | expand

Commit Message

Murthy, Arun R Aug. 27, 2024, 8:12 a.m. UTC
UHBR20 is not supported by battlemage and the maximum link rate
supported is UHBR13.5

v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)

HSD: 16023263677
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Comments

Kahola, Mika Aug. 27, 2024, 12:54 p.m. UTC | #1
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Arun R Murthy
> Sent: Tuesday, August 27, 2024 11:12 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: [PATCHv2] drm/i915/display: BMG supports UHBR13.5
> 
> UHBR20 is not supported by battlemage and the maximum link rate supported is
> UHBR13.5
> 
> v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
> 
> HSD: 16023263677

Looks ok to me.

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 789c2f78826d..99a365a945ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -528,6 +528,10 @@ static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)  {
>  	/* The values must be in increasing order */
> +	static const int bmg_rates[] = {
> +		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> +		810000,	1000000, 1350000,
> +	};
>  	static const int mtl_rates[] = {
>  		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>  		810000,	1000000, 2000000,
> @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		    intel_dp->source_rates || intel_dp->num_source_rates);
> 
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> -		source_rates = mtl_rates;
> -		size = ARRAY_SIZE(mtl_rates);
> +		if (IS_BATTLEMAGE(dev_priv)) {
> +			source_rates = bmg_rates;
> +			size = ARRAY_SIZE(bmg_rates);
> +		} else {
> +			source_rates = mtl_rates;
> +			size = ARRAY_SIZE(mtl_rates);
> +		}
>  		max_rate = mtl_max_source_rate(intel_dp);
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		source_rates = icl_rates;
> --
> 2.25.1
Govindapillai, Vinod Aug. 28, 2024, 10:02 a.m. UTC | #2
Hi,

Do we need this? There is this patch already https://patchwork.freedesktop.org/patch/592161/

Looks like we are supposed to iterate source_rates using "intel_dp->num_source_rates"

If you are keeping this, then may be we need a separate max_rate call for bmg for better clarity?
Now there is a separate source_rates for bmg but a max_rate using mtl_max_rate()!

BR
Vinod


On Tue, 2024-08-27 at 13:42 +0530, Arun R Murthy wrote:
> UHBR20 is not supported by battlemage and the maximum link rate
> supported is UHBR13.5
> 
> v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
> 
> HSD: 16023263677
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 789c2f78826d..99a365a945ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -528,6 +528,10 @@ static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>         /* The values must be in increasing order */
> +       static const int bmg_rates[] = {
> +               162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> +               810000, 1000000, 1350000,
> +       };
>         static const int mtl_rates[] = {
>                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>                 810000, 1000000, 2000000,
> @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>                     intel_dp->source_rates || intel_dp->num_source_rates);
>  
>         if (DISPLAY_VER(dev_priv) >= 14) {
> -               source_rates = mtl_rates;
> -               size = ARRAY_SIZE(mtl_rates);
> +               if (IS_BATTLEMAGE(dev_priv)) {
> +                       source_rates = bmg_rates;
> +                       size = ARRAY_SIZE(bmg_rates);
> +               } else {
> +                       source_rates = mtl_rates;
> +                       size = ARRAY_SIZE(mtl_rates);
> +               }
>                 max_rate = mtl_max_source_rate(intel_dp);
>         } else if (DISPLAY_VER(dev_priv) >= 11) {
>                 source_rates = icl_rates;
Jani Nikula Aug. 28, 2024, 11:21 a.m. UTC | #3
On Wed, 28 Aug 2024, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> Hi,
>
> Do we need this? There is this patch already https://patchwork.freedesktop.org/patch/592161/

mtl_rates doesn't have 1350000.

BR,
Jani.

>
> Looks like we are supposed to iterate source_rates using "intel_dp->num_source_rates"
>
> If you are keeping this, then may be we need a separate max_rate call for bmg for better clarity?
> Now there is a separate source_rates for bmg but a max_rate using mtl_max_rate()!
>
> BR
> Vinod
>
>
> On Tue, 2024-08-27 at 13:42 +0530, Arun R Murthy wrote:
>> UHBR20 is not supported by battlemage and the maximum link rate
>> supported is UHBR13.5
>> 
>> v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
>> 
>> HSD: 16023263677
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>>  1 file changed, 11 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 789c2f78826d..99a365a945ae 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -528,6 +528,10 @@ static void
>>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  {
>>         /* The values must be in increasing order */
>> +       static const int bmg_rates[] = {
>> +               162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>> +               810000, 1000000, 1350000,
>> +       };
>>         static const int mtl_rates[] = {
>>                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>>                 810000, 1000000, 2000000,
>> @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>                     intel_dp->source_rates || intel_dp->num_source_rates);
>>  
>>         if (DISPLAY_VER(dev_priv) >= 14) {
>> -               source_rates = mtl_rates;
>> -               size = ARRAY_SIZE(mtl_rates);
>> +               if (IS_BATTLEMAGE(dev_priv)) {
>> +                       source_rates = bmg_rates;
>> +                       size = ARRAY_SIZE(bmg_rates);
>> +               } else {
>> +                       source_rates = mtl_rates;
>> +                       size = ARRAY_SIZE(mtl_rates);
>> +               }
>>                 max_rate = mtl_max_source_rate(intel_dp);
>>         } else if (DISPLAY_VER(dev_priv) >= 11) {
>>                 source_rates = icl_rates;
>
Jani Nikula Aug. 29, 2024, 12:19 p.m. UTC | #4
On Tue, 27 Aug 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> UHBR20 is not supported by battlemage and the maximum link rate
> supported is UHBR13.5
>
> v2: Replace IS_DGFX with IS_BATTLEMAGE (Jani)
>
> HSD: 16023263677
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>

Also,

Fixes: 98b1c87a5e51 ("drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5")

because that one doesn't DTRT.

BR,
Jani.




> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 789c2f78826d..99a365a945ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -528,6 +528,10 @@ static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	/* The values must be in increasing order */
> +	static const int bmg_rates[] = {
> +		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> +		810000,	1000000, 1350000,
> +	};
>  	static const int mtl_rates[] = {
>  		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
>  		810000,	1000000, 2000000,
> @@ -558,8 +562,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		    intel_dp->source_rates || intel_dp->num_source_rates);
>  
>  	if (DISPLAY_VER(dev_priv) >= 14) {
> -		source_rates = mtl_rates;
> -		size = ARRAY_SIZE(mtl_rates);
> +		if (IS_BATTLEMAGE(dev_priv)) {
> +			source_rates = bmg_rates;
> +			size = ARRAY_SIZE(bmg_rates);
> +		} else {
> +			source_rates = mtl_rates;
> +			size = ARRAY_SIZE(mtl_rates);
> +		}
>  		max_rate = mtl_max_source_rate(intel_dp);
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
>  		source_rates = icl_rates;
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 789c2f78826d..99a365a945ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -528,6 +528,10 @@  static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
 	/* The values must be in increasing order */
+	static const int bmg_rates[] = {
+		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
+		810000,	1000000, 1350000,
+	};
 	static const int mtl_rates[] = {
 		162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 		810000,	1000000, 2000000,
@@ -558,8 +562,13 @@  intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		    intel_dp->source_rates || intel_dp->num_source_rates);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
-		source_rates = mtl_rates;
-		size = ARRAY_SIZE(mtl_rates);
+		if (IS_BATTLEMAGE(dev_priv)) {
+			source_rates = bmg_rates;
+			size = ARRAY_SIZE(bmg_rates);
+		} else {
+			source_rates = mtl_rates;
+			size = ARRAY_SIZE(mtl_rates);
+		}
 		max_rate = mtl_max_source_rate(intel_dp);
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
 		source_rates = icl_rates;