| Message ID | 20240911151836.16800-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | drm/i915/psr: Fix PSR sink enable sequence | expand |
On Wed, Sep 11, 2024 at 08:28:09PM -0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: Fix PSR sink enable sequence > URL : https://patchwork.freedesktop.org/series/138530/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_15395 -> Patchwork_138530v1 > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_138530v1 absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_138530v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138530v1/index.html > > Participating hosts (40 -> 36) > ------------------------------ > > Additional (2): bat-mtlp-8 fi-kbl-8809g > Missing (6): fi-kbl-7567u bat-kbl-2 fi-snb-2520m fi-glk-j4005 bat-dg2-11 bat-mtlp-6 > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in Patchwork_138530v1: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@i915_selftest@live@gt_pm: > - bat-twl-1: [PASS][1] -> [DMESG-FAIL][2] +1 other test dmesg-fail > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15395/bat-twl-1/igt@i915_selftest@live@gt_pm.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138530v1/bat-twl-1/igt@i915_selftest@live@gt_pm.html <3> [283.360457] No power measured while in RC0 <3> [283.360544] i915/intel_gt_pm_live_selftests: live_rc6_manual failed with error -22 Unrelated to this change.
Quoting Ville Syrjala (2024-09-11 12:18:36-03:00) >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > >According to the eDP spec, the source must first configure all >PSR related DPCD registers apart from the actual enable bit, >and only then set the enable bit. Split the current single DPCD >write to two to match the spec. > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> >--- > drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > >diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c >index 1a4ef231a53c..2b7c0c73f335 100644 >--- a/drivers/gpu/drm/i915/display/intel_psr.c >+++ b/drivers/gpu/drm/i915/display/intel_psr.c >@@ -745,7 +745,7 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(intel_dp); >- u8 val = DP_PSR_ENABLE; >+ u8 val = 0; > > if (crtc_state->has_sel_update) { > val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; >@@ -765,7 +765,9 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, > > if (intel_dp->psr.entry_setup_frames > 0) > val |= DP_PSR_FRAME_CAPTURE; >+ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); > >+ val |= DP_PSR_ENABLE; > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); > } > >-- >2.44.2 >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1a4ef231a53c..2b7c0c73f335 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -745,7 +745,7 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - u8 val = DP_PSR_ENABLE; + u8 val = 0; if (crtc_state->has_sel_update) { val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; @@ -765,7 +765,9 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, if (intel_dp->psr.entry_setup_frames > 0) val |= DP_PSR_FRAME_CAPTURE; + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); + val |= DP_PSR_ENABLE; drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); }