Message ID | 20240912050552.779356-3-arun.r.murthy@intel.com (mailing list archive) |
---|---|
State | New |
Headers | show |
Series | Some correction in the DP Link Training dequence | expand |
On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote: > DP Source should be reading AUX_RD interval after we get adjusted > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting > in DP Source) Please explain why. BR, Jani. > > Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> > --- > .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index f41b69840ad9..ca179bed46ad 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, > for (try = 0; try < max_tries; try++) { > fsleep(delay_us); > > - /* > - * The delay may get updated. The transmitter shall read the > - * delay before link status during link training. > - */ > - delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); > - > if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { > lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); > return false; > @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, > lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); > return false; > } > + > + /* > + * The delay may get updated. The transmitter shall read the > + * delay before link status during link training. > + */ > + delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); > } > > if (try == max_tries) {
> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote: > > DP Source should be reading AUX_RD interval after we get adjusted > > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in DP > > Source) > > Please explain why. As per the DP 2.1 spec section 3.5.2.16.1 "The transmitter shall finish reading from DPCD 00202h through 00207h, DPCD 0200Ch through 0200Fh, and DPCD 02216h, and writing to DPCD 00103h through 00106h (listed as "AUX TX response" in Figure 3-51) within 2.5 ms or less, such that the total duration for AUX TX responses with a 20-loop count does not exceed 50 ms. " Thanks and Regards, Arun R Murthy --------------------
Hi Jani, It's as per DP2.1 spec, where we should be reading AUX_RD interval at the loop before we wait. [cid:image001.png@01DB0538.65998930] Regards Srikanth -----Original Message----- From: Murthy, Arun R <arun.r.murthy@intel.com> Sent: Thursday, September 12, 2024 4:25 PM To: Jani Nikula <jani.nikula@linux.intel.com>; intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org Cc: Srikanth V, NagaVenkata <nagavenkata.srikanth.v@intel.com> Subject: RE: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset > On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com<mailto:arun.r.murthy@intel.com>> wrote: > > DP Source should be reading AUX_RD interval after we get adjusted > > TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting in > > DP > > Source) > > Please explain why. As per the DP 2.1 spec section 3.5.2.16.1 "The transmitter shall finish reading from DPCD 00202h through 00207h, DPCD 0200Ch through 0200Fh, and DPCD 02216h, and writing to DPCD 00103h through 00106h (listed as "AUX TX response" in Figure 3-51) within 2.5 ms or less, such that the total duration for AUX TX responses with a 20-loop count does not exceed 50 ms. " Thanks and Regards, Arun R Murthy --------------------
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index f41b69840ad9..ca179bed46ad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, for (try = 0; try < max_tries; try++) { fsleep(delay_us); - /* - * The delay may get updated. The transmitter shall read the - * delay before link status during link training. - */ - delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); - if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); return false; @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); return false; } + + /* + * The delay may get updated. The transmitter shall read the + * delay before link status during link training. + */ + delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); } if (try == max_tries) {