@@ -2934,6 +2934,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
enum phy phy = intel_encoder_to_phy(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2948,10 +2949,9 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_lane_reset(encoder, lane_reversal);
/*
- * 3. Change Phy power state to Ready.
- * TODO: For DP alt mode use only one lane.
+ * 3. Change Phy power state to Ready on owned lanes.
*/
- intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
+ intel_cx0_powerdown_change_sequence(encoder, owned_lane_mask,
CX0_P2_STATE_READY);
/*
In DP alt mode, when pin assignment is D, only one PHY lane is owned by the display. intel_cx0pll_enable currently performs a power state ready on both the lanes in all cases. Address the todo to perfom power state ready on owned lanes. Tested on Meteor Lake-P [Intel Arc Graphics] with DP alt mode. v2 -> v3: - Fix changelog per Jani Nikula's feedback v1 -> v2: Address Gustavo Sousa's feedback - Use owned lanes mask to set Phy power state to Ready, instead of maxpclk_lane with DP alt mode check. - Owned lanes are obtained from intel_cx0_get_owned_lane_mask(). Signed-off-by: Vamsi Krishna Brahmajosyula <vamsikrishna.brahmajosyula@gmail.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) base-commit: ad060dbbcfcfcba624ef1a75e1d71365a98b86d8