| Message ID | 20240923043205.2016070-3-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implement Wa 14019834836 | expand |
Quoting Jouni Högander (2024-09-23 01:32:05-03:00) >This patch implements HW workaround 14019834836 for display version >= 30. > >Signed-off-by: Jouni Högander <jouni.hogander@intel.com> >--- > drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > >diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c >index f7dfd9435b589..e529132da93a4 100644 >--- a/drivers/gpu/drm/i915/display/intel_psr.c >+++ b/drivers/gpu/drm/i915/display/intel_psr.c >@@ -2493,6 +2493,8 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); >+ struct intel_encoder *encoder; >+ int hactive_limit; > > /* Wa_14014971492 */ > if (!crtc_state->has_panel_replay && >@@ -2500,6 +2502,34 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) > IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && > crtc_state->splitter.enable) > crtc_state->psr2_su_area.y1 = 0; >+ >+ /* Rest of the function is for Wa 14019834836 */ >+ if (DISPLAY_VER(display) < 30) >+ return; Should we really have the expectation that this workaround would extend to future display IPs? Maybe it might be better to use an equality check here, just so that we do not accidentally apply this to a future display release that might have the bug fixed. In that case, I would have the workaround logic in a separate function and call it only for DISPLAY_VER(display) == 30. -- Gustavo Sousa >+ >+ if (crtc_state->psr2_su_area.y1 != 0 || >+ crtc_state->psr2_su_area.y2 != 0) >+ return; >+ >+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) >+ hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; >+ else >+ hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; >+ >+ if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) >+ return; >+ >+ for_each_intel_encoder_mask_with_psr(display->drm, encoder, >+ crtc_state->uapi.encoder_mask) { >+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder); >+ >+ if (!intel_dp_is_edp(intel_dp) && >+ intel_dp->psr.panel_replay_enabled && >+ intel_dp->psr.sel_update_enabled) { >+ crtc_state->psr2_su_area.y2++; >+ return; >+ } >+ } > } > > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, >-- >2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f7dfd9435b589..e529132da93a4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2493,6 +2493,8 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_encoder *encoder; + int hactive_limit; /* Wa_14014971492 */ if (!crtc_state->has_panel_replay && @@ -2500,6 +2502,34 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; + + /* Rest of the function is for Wa 14019834836 */ + if (DISPLAY_VER(display) < 30) + return; + + if (crtc_state->psr2_su_area.y1 != 0 || + crtc_state->psr2_su_area.y2 != 0) + return; + + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; + else + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; + + if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) + return; + + for_each_intel_encoder_mask_with_psr(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (!intel_dp_is_edp(intel_dp) && + intel_dp->psr.panel_replay_enabled && + intel_dp->psr.sel_update_enabled) { + crtc_state->psr2_su_area.y2++; + return; + } + } } int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
This patch implements HW workaround 14019834836 for display version >= 30. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+)