From patchwork Tue Sep 24 06:13:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arun R Murthy X-Patchwork-Id: 13810179 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F7C1CF9C71 for ; Tue, 24 Sep 2024 06:24:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4429510E4DF; Tue, 24 Sep 2024 06:24:05 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G3bR5Smx"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4F0BB10E4DE; Tue, 24 Sep 2024 06:24:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1727159042; x=1758695042; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xey4x6KhJR3mRRIWA27Ij73G0qXRksgDMLxciYEnPHA=; b=G3bR5SmxTkZeQ7S0DFchFs8lR3eex0GgoNuVNvDHbt+jtcIotIqUL+5S 4RSWT6IFZyqPNguP40KCBHAvLgWM38umHaSYZ413kTV/d5LgfQYfBN8cj 4IlNTpdJSjUYcXWSl4SeR1K1smcmcKYspkS2Hfz5jjvDNRiTwKt3eBpy3 Dioul0D0uzFLc6GI/d94YDQ/bZ3aignHqSzBsTEeajXSqdzSgNVf+CVid +X4gmzPl1skbCX29rYJZ31keAWr20MGKIbSN8pDQ/Q/wVdjo21bHEubgr b7SAf2VDrSW5p+QjTW+//ewEAzIee3j30/k15xQ7Qi1iPCJmds2G+tgus A==; X-CSE-ConnectionGUID: 8urZopigQKeRKR+SwAxkMA== X-CSE-MsgGUID: 52BCvHjeRH6urWkUadRG8w== X-IronPort-AV: E=McAfee;i="6700,10204,11204"; a="26229887" X-IronPort-AV: E=Sophos;i="6.10,253,1719903600"; d="scan'208";a="26229887" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2024 23:24:02 -0700 X-CSE-ConnectionGUID: 96ThOFX0TZC+egCJg2Vg3A== X-CSE-MsgGUID: q5eUPPvySFCQZYhre0tt3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,253,1719903600"; d="scan'208";a="76086149" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orviesa003.jf.intel.com with ESMTP; 23 Sep 2024 23:24:00 -0700 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Arun R Murthy , Srikanth V NagaVenkata , Suraj Kandpal , Jani Nikula Subject: [PATCHv2 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout Date: Tue, 24 Sep 2024 11:43:58 +0530 Message-Id: <20240924061358.1725306-4-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240924061358.1725306-1-arun.r.murthy@intel.com> References: <20240924061358.1725306-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this timeout value is exclusively for the Aux RD Interval and excludes the time consumed for the AUX Tx (i.e reading/writing FFE presets). Add another 50ms for these AUX Tx to the 400ms timeout. Ref: "Figure 3-52: 128b132b DP DPTC LANEx_CHANNEL_EQ_DONE Sequence" of DP2.1a spec. Co-developed-by: Srikanth V NagaVenkata Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 460426a3b506..60bf375b9aec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, } /* Time budget for the LANEx_EQ_DONE Sequence */ - deadline = jiffies + msecs_to_jiffies_timeout(400); + deadline = jiffies + msecs_to_jiffies_timeout(450); for (try = 0; try < max_tries; try++) { fsleep(delay_us);