diff mbox series

drm/i915/vdsc: Add bpc check in intel_dsc_compute_params

Message ID 20240926053346.1391776-2-suraj.kandpal@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/vdsc: Add bpc check in intel_dsc_compute_params | expand

Commit Message

Kandpal, Suraj Sept. 26, 2024, 5:33 a.m. UTC
DSC does not support bpc under 8 according to DSC 1.2a Section 2
Requirements. Return an error if that happens to be the case.

--v2
-should be bits_per_component [Mitul/Chaitanya/Srikanth]
-Add reference to this restriction [Chaitanya]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Chaitanya Kumar Borah Sept. 26, 2024, 5:52 a.m. UTC | #1
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Thursday, September 26, 2024 11:04 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH] drm/i915/vdsc: Add bpc check in
> intel_dsc_compute_params
> 
> DSC does not support bpc under 8 according to DSC 1.2a Section 2
> Requirements. Return an error if that happens to be the case.
> 
> --v2
> -should be bits_per_component [Mitul/Chaitanya/Srikanth] -Add reference to
> this restriction [Chaitanya]
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

LGTM


Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 8158e3702ed5..7a30fdea16da 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -306,6 +306,11 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
> 
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> 
> +	if (vdsc_cfg->bits_per_component < 8) {
> +		drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not
> met\n");
> +		return -EINVAL;
> +	}
> +
>  	drm_dsc_set_rc_buf_thresh(vdsc_cfg);
> 
>  	/*
> --
> 2.43.2
Jani Nikula Sept. 26, 2024, 7:59 a.m. UTC | #2
On Thu, 26 Sep 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> DSC does not support bpc under 8 according to DSC 1.2a Section 2
> Requirements. Return an error if that happens to be the case.
>
> --v2
> -should be bits_per_component [Mitul/Chaitanya/Srikanth]
> -Add reference to this restriction [Chaitanya]
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 8158e3702ed5..7a30fdea16da 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -306,6 +306,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>  
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
>  
> +	if (vdsc_cfg->bits_per_component < 8) {
> +		drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met\n");

If you hit this warning, what's the absolutely first thing you want to
know...? Maybe log that bits_per_component value here?

BR,
Jani.

> +		return -EINVAL;
> +	}
> +
>  	drm_dsc_set_rc_buf_thresh(vdsc_cfg);
>  
>  	/*
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8158e3702ed5..7a30fdea16da 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -306,6 +306,11 @@  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
+	if (vdsc_cfg->bits_per_component < 8) {
+		drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met\n");
+		return -EINVAL;
+	}
+
 	drm_dsc_set_rc_buf_thresh(vdsc_cfg);
 
 	/*