| Message ID | 20240926072638.3689367-12-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Ultrajoiner basic functionality series | expand |
On Thu, Sep 26, 2024 at 12:56:34PM +0530, Ankit Nautiyal wrote: > Add compressed bpp limitations for ultrajoiner. > > v2: Fix the case for 1 pipe. (Ankit) > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++------ > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index f2a2541c1091..a0afb4991334 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -865,24 +865,39 @@ u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, > int num_joined_pipes) > { > u32 max_bpp_small_joiner_ram; > + u32 max_bpp_bigjoiner; > + u32 max_bpp; > > /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ > max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; > > - if (num_joined_pipes == 2) { > + if (num_joined_pipes == 1) > + return max_bpp_small_joiner_ram; Hmm. This seems to assume that small joiner will be enabled. I can't immediately see anything that would guarantee that is the case. But I suppose it's a safe assumption in that we can then freely choose whether to use small joiner or not based on other constraints. > + > + if (num_joined_pipes > 1) { > int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ > int ppc = 2; > - u32 max_bpp_bigjoiner = > - i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / > + int num_bigjoiners = num_joined_pipes / 2; > + > + max_bpp_bigjoiner = > + i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits * The the '/' seems to have turned into a '*'. > intel_dp_mode_to_fec_clock(mode_clock); > > - max_bpp_small_joiner_ram *= 2; > + max_bpp_bigjoiner *= num_bigjoiners; > + > + max_bpp_small_joiner_ram *= num_joined_pipes; I get the feeling we're not handling the MSO overlap properly in this code. But that's not directly related to this patch I guess. I think we need to split this function up into its constituent parts. Right now it's mixing it all into a big mush that's very hard to follow. Once that is done this function should just collapse into: max_bpp = min(max_bpp, smalljoiner_ram_max_bpp()) max_bpp = min(max_bpp, bigjoiner_bw_max_bpp()) max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp()) We should also extract functions for bigjoiner_interface_bits() and ultrajoiner_ram_size_bits() so that we don't have to be distracted by the actual numbers. > + } > + > + max_bpp = min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); > + > + if (num_joined_pipes == 4) { > + u32 max_bpp_ultrajoiner_ram = (4 * 72 * 512) / mode_hdisplay; > > - return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); > + max_bpp = min(max_bpp, max_bpp_ultrajoiner_ram); > } > > - return max_bpp_small_joiner_ram; > + return max_bpp; > } > > u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, > -- > 2.45.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f2a2541c1091..a0afb4991334 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -865,24 +865,39 @@ u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, int num_joined_pipes) { u32 max_bpp_small_joiner_ram; + u32 max_bpp_bigjoiner; + u32 max_bpp; /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; - if (num_joined_pipes == 2) { + if (num_joined_pipes == 1) + return max_bpp_small_joiner_ram; + + if (num_joined_pipes > 1) { int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ int ppc = 2; - u32 max_bpp_bigjoiner = - i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits / + int num_bigjoiners = num_joined_pipes / 2; + + max_bpp_bigjoiner = + i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits * intel_dp_mode_to_fec_clock(mode_clock); - max_bpp_small_joiner_ram *= 2; + max_bpp_bigjoiner *= num_bigjoiners; + + max_bpp_small_joiner_ram *= num_joined_pipes; + } + + max_bpp = min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); + + if (num_joined_pipes == 4) { + u32 max_bpp_ultrajoiner_ram = (4 * 72 * 512) / mode_hdisplay; - return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); + max_bpp = min(max_bpp, max_bpp_ultrajoiner_ram); } - return max_bpp_small_joiner_ram; + return max_bpp; } u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
Add compressed bpp limitations for ultrajoiner. v2: Fix the case for 1 pipe. (Ankit) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-)