diff mbox series

[v2,07/10] drm/i915/xe3lpd: Add C20 Phy consolidated programming table

Message ID 20241010224311.50133-8-matthew.s.atwood@intel.com (mailing list archive)
State New
Headers show
Series Add xe3lpd edp enabling | expand

Commit Message

Matt Atwood Oct. 10, 2024, 10:43 p.m. UTC 
From: Suraj Kandpal <suraj.kandpal@intel.com>

From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
DP and eDP been merged and now use the same rates and values. eDP
over TypeC has also been introduced.
Moreover it allows more granular and higher rates. Add new table to
represent this change.

Bspec: 68961
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24 ++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

Comments

Matt Roper Oct. 11, 2024, 9:45 p.m. UTC | #1 
On Thu, Oct 10, 2024 at 03:43:08PM -0700, Matt Atwood wrote:
> From: Suraj Kandpal <suraj.kandpal@intel.com>
> 
> From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of
> DP and eDP been merged and now use the same rates and values. eDP
> over TypeC has also been introduced.
> Moreover it allows more granular and higher rates. Add new table to
> represent this change.
> 
> Bspec: 68961
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24 ++++++++++++++++++--
>  1 file changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f73d576fd99e..f1aea5ead41b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
>  	NULL,
>  };
>  
> +static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
> +	&mtl_c20_dp_rbr,
> +	&xe2hpd_c20_edp_r216,
> +	&xe2hpd_c20_edp_r243,
> +	&mtl_c20_dp_hbr1,
> +	&xe2hpd_c20_edp_r324,
> +	&xe2hpd_c20_edp_r432,
> +	&mtl_c20_dp_hbr2,
> +	&xe2hpd_c20_edp_r675,
> +	&mtl_c20_dp_hbr3,
> +	&mtl_c20_dp_uhbr10,
> +	&xe2hpd_c20_dp_uhbr13_5,
> +	&mtl_c20_dp_uhbr20,
> +	NULL,
> +};
> +
>  /*
>   * HDMI link rates with 38.4 MHz reference clock.
>   */
> @@ -2242,11 +2258,15 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> -			return xe2hpd_c20_edp_tables;
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +			if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))

It might be a bit simpler to && the conditions here instead of nesting
if's.

> +				return xe2hpd_c20_edp_tables;
> +		}
>  
>  		if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
>  			return xe2hpd_c20_dp_tables;
> +		else if (DISPLAY_VER(i915) >= 30)

Shouldn't this ladder be using the standard "newest platform first"
ordering?


Matt

> +			return xe3lpd_c20_dp_edp_tables;
>  		else
>  			return mtl_c20_dp_tables;
>  
> -- 
> 2.45.0
>
Kandpal, Suraj Oct. 13, 2024, 3:23 p.m. UTC | #2 
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Saturday, October 12, 2024 3:16 AM
> To: Atwood, Matthew S <matthew.s.atwood@intel.com>
> Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Kandpal,
> Suraj <suraj.kandpal@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>
> Subject: Re: [PATCH v2 07/10] drm/i915/xe3lpd: Add C20 Phy consolidated
> programming table
> 
> On Thu, Oct 10, 2024 at 03:43:08PM -0700, Matt Atwood wrote:
> > From: Suraj Kandpal <suraj.kandpal@intel.com>
> >
> > From DISPLAY_VER() >= 30 C20 PHY consolidated programming table of DP
> > and eDP been merged and now use the same rates and values. eDP over
> > TypeC has also been introduced.
> > Moreover it allows more granular and higher rates. Add new table to
> > represent this change.
> >
> > Bspec: 68961
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 24
> > ++++++++++++++++++--
> >  1 file changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index f73d576fd99e..f1aea5ead41b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -1122,6 +1122,22 @@ static const struct intel_c20pll_state * const
> xe2hpd_c20_dp_tables[] = {
> >  	NULL,
> >  };
> >
> > +static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[]
> = {
> > +	&mtl_c20_dp_rbr,
> > +	&xe2hpd_c20_edp_r216,
> > +	&xe2hpd_c20_edp_r243,
> > +	&mtl_c20_dp_hbr1,
> > +	&xe2hpd_c20_edp_r324,
> > +	&xe2hpd_c20_edp_r432,
> > +	&mtl_c20_dp_hbr2,
> > +	&xe2hpd_c20_edp_r675,
> > +	&mtl_c20_dp_hbr3,
> > +	&mtl_c20_dp_uhbr10,
> > +	&xe2hpd_c20_dp_uhbr13_5,
> > +	&mtl_c20_dp_uhbr20,
> > +	NULL,
> > +};
> > +
> >  /*
> >   * HDMI link rates with 38.4 MHz reference clock.
> >   */
> > @@ -2242,11 +2258,15 @@ intel_c20_pll_tables_get(struct intel_crtc_state
> *crtc_state,
> >  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >
> >  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> > -		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > -			return xe2hpd_c20_edp_tables;
> > +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> > +			if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> 
> It might be a bit simpler to && the conditions here instead of nesting if's.

I kept it like this because in the next patch I add a condition for edp over type c 

> 
> > +				return xe2hpd_c20_edp_tables;
> > +		}
> >
> >  		if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> >  			return xe2hpd_c20_dp_tables;
> > +		else if (DISPLAY_VER(i915) >= 30)
> 
> Shouldn't this ladder be using the standard "newest platform first"
> ordering?

Sure will add that change

Regards,
Suraj Kandpal
> 
> 
> Matt
> 
> > +			return xe3lpd_c20_dp_edp_tables;
> >  		else
> >  			return mtl_c20_dp_tables;
> >
> > --
> > 2.45.0
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f73d576fd99e..f1aea5ead41b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1122,6 +1122,22 @@  static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
 	NULL,
 };
 
+static const struct intel_c20pll_state * const xe3lpd_c20_dp_edp_tables[] = {
+	&mtl_c20_dp_rbr,
+	&xe2hpd_c20_edp_r216,
+	&xe2hpd_c20_edp_r243,
+	&mtl_c20_dp_hbr1,
+	&xe2hpd_c20_edp_r324,
+	&xe2hpd_c20_edp_r432,
+	&mtl_c20_dp_hbr2,
+	&xe2hpd_c20_edp_r675,
+	&mtl_c20_dp_hbr3,
+	&mtl_c20_dp_uhbr10,
+	&xe2hpd_c20_dp_uhbr13_5,
+	&mtl_c20_dp_uhbr20,
+	NULL,
+};
+
 /*
  * HDMI link rates with 38.4 MHz reference clock.
  */
@@ -2242,11 +2258,15 @@  intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
-			return xe2hpd_c20_edp_tables;
+		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+			if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+				return xe2hpd_c20_edp_tables;
+		}
 
 		if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
 			return xe2hpd_c20_dp_tables;
+		else if (DISPLAY_VER(i915) >= 30)
+			return xe3lpd_c20_dp_edp_tables;
 		else
 			return mtl_c20_dp_tables;