From patchwork Mon Oct 21 22:27:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Sousa X-Patchwork-Id: 13844791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D9ADD17141 for ; Mon, 21 Oct 2024 22:28:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6ADD10E5C6; Mon, 21 Oct 2024 22:28:13 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="T80eArmm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id B62C110E5C0; Mon, 21 Oct 2024 22:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729549689; x=1761085689; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZvSHELlRQpgaJXCjnTADEhbydhF4Wl2ard2i+v8W5AA=; b=T80eArmmRHhQD4/xF8G7oHLO9r0jn3IwfFnDSPvmc+suHOoPtWoH/Cnn c75kdMJLok3Iwk6gjoi/zVXitfjcgT3/ZYKaHcDP/vKNHo1B/5SFUDWgB d6CSmajDwRr44r61QGeM1NC2n0CZMbxbWKhMkSEfAKfUGHX45dngUVrbu 2r5E/PpDxNkvw2ojy5/zCNNA1zZBxKsBsCvlvou4hcR6kOlMdrmQVLLFr qyAnZPPd29pmKzbaaONrN1NZ/ha7IwGndw6wGVkslyFNfYhtSHAUCY4el E5UIOdMDFh6rK/p/QL7s33uqoV7vAHcUKhr2V/CxnNAQOz+/qoN9vOkqv Q==; X-CSE-ConnectionGUID: /muoYMsxQbGUl4a5IdQyjg== X-CSE-MsgGUID: huGwdrMpSV6zvNWga5Ik6A== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="28934458" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="28934458" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 15:28:09 -0700 X-CSE-ConnectionGUID: bx+iDMPCT6GBcOndZttGjw== X-CSE-MsgGUID: QrM2BKWzRX2j7FlPYpi9JQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,221,1725346800"; d="scan'208";a="80009608" Received: from aschofie-mobl2.amr.corp.intel.com (HELO gjsousa-mobl2.intel.com) ([10.125.110.79]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2024 15:28:07 -0700 From: Gustavo Sousa To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Luca Coelho , Rodrigo Vivi Subject: [PATCH 05/13] drm/i915/dmc_wl: Use sentinel item for range tables Date: Mon, 21 Oct 2024 19:27:24 -0300 Message-ID: <20241021222744.294371-6-gustavo.sousa@intel.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241021222744.294371-1-gustavo.sousa@intel.com> References: <20241021222744.294371-1-gustavo.sousa@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We are currently using ARRAY_SIZE() to iterate address ranges in intel_dmc_wl_check_range(). In upcoming changes, we will be using more than a single table and will extract the range checking logic into a dedicated function that takes a range table as argument. As we will not able to use ARRAY_SIZE() then, let's make range tables contain a sentinel item at the end and use that instead of having to pass the size as parameter in this future function. Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 5ed610c9be39..82eb9166e5f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -49,6 +49,7 @@ struct intel_dmc_wl_range { static struct intel_dmc_wl_range lnl_wl_range[] = { { .start = 0x60000, .end = 0x7ffff }, + {}, }; static void __intel_dmc_wl_release(struct intel_display *display) @@ -99,7 +100,7 @@ static bool intel_dmc_wl_check_range(u32 address) int i; bool wl_needed = false; - for (i = 0; i < ARRAY_SIZE(lnl_wl_range); i++) { + for (i = 0; lnl_wl_range[i].start; i++) { if (address >= lnl_wl_range[i].start && address <= lnl_wl_range[i].end) { wl_needed = true;