@@ -5762,6 +5762,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(dsc.num_streams);
PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
PIPE_CONF_CHECK_I(dsc.replicated_pixels);
+ PIPE_CONF_CHECK_BOOL(dsc.has_odd_pixel);
PIPE_CONF_CHECK_BOOL(splitter.enable);
PIPE_CONF_CHECK_I(splitter.link_count);
@@ -1235,6 +1235,7 @@ struct intel_crtc_state {
/* Display Stream compression state */
struct {
bool compression_enable;
+ bool has_odd_pixel;
int num_streams;
/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
u16 compressed_bpp_x16;
@@ -797,6 +797,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
}
+ if (crtc_state->dsc.has_odd_pixel) {
+ dss_ctl2_val |= ODD_PIXEL_REMOVAL;
+ if (crtc->pipe == PIPE_A || crtc->pipe == PIPE_C)
+ dss_ctl2_val |= ODD_PIXEL_REMOVAL_CONFIG_EOL;
+ }
+
if (crtc_state->dsc.replicated_pixels)
dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.replicated_pixels);
@@ -1011,6 +1017,9 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
crtc_state->dsc.num_streams = 0;
}
+ if (dss_ctl2 & ODD_PIXEL_REMOVAL)
+ crtc_state->dsc.has_odd_pixel = true;
+
if (dss_ctl3 & DSC_PIXEL_REPLICATION_MASK)
crtc_state->dsc.replicated_pixels =
dss_ctl3 & DSC_PIXEL_REPLICATION_MASK;
@@ -24,6 +24,8 @@
#define VDSC0_ENABLE REG_BIT(31)
#define VDSC2_ENABLE REG_BIT(30)
#define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
+#define ODD_PIXEL_REMOVAL REG_BIT(18)
+#define ODD_PIXEL_REMOVAL_CONFIG_EOL REG_BIT(17)
#define VDSC1_ENABLE REG_BIT(15)
#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
With 3 DSC engines we can support 12 slices. With ultra joiner usecase while dividing the width into 12 slices, we might end up having odd number of pixels per pipe. As per Bspec, pipe src size should be even, so an extra pixel is added in each pipe. For Pipe A and C the odd pixel is added at the end of pipe and for Pipe B and D it is added at the beginning of the pipe. This extra pixel needs to be dropped in Splitter hardware. Introduce bits to account for odd pixel removal while programming DSS CTL. Add a new member in crtc state to track if we need to account for the odd pixel. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_vdsc.c | 9 +++++++++ drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 ++ 4 files changed, 13 insertions(+)