From patchwork Wed Oct 23 21:46:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Clint Taylor X-Patchwork-Id: 13848003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D23A0D0BB4B for ; Wed, 23 Oct 2024 21:47:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0416A10E885; Wed, 23 Oct 2024 21:47:11 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="iugTm9j9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id B1EB510E86E; Wed, 23 Oct 2024 21:47:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1729720027; x=1761256027; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3vPXdU0VlQ2VBfIfWbAN2Ehl4Fsmhpra1TFXgc/ht4E=; b=iugTm9j9wsvPUOp6j2Z6/hcu0NiA7ssbRACYuy96bhnag5nEgi0nBhvW BmYVE/26xuK+F3vzJmJk19SCkgnBJbDHIKl0OGDAZT/VqIjbtJ9XYMcKe mq+zQKOLCbunprHm/dJ9WdqooFwtP6sCB8MwTzadPWEksEl32stwOB5Xa rbUUta7rGhSiBuUNzMGnLAsJa5pH3IrBeBZ1dszheaR+wqc4w4zB61ggz W2s5gLlViOjeJKR3uFSlg5mM9I6CDX5ttUPn7uYkPZkB/3psu5V9pzLUo FDtgdSw4uPQxMUs6B3tk5USWups9hwkMxTb67SRv3lec2ZgDxl5fuojh5 g==; X-CSE-ConnectionGUID: o+tK56KWQ7OP5Vq46cnbyQ== X-CSE-MsgGUID: w0j0ZH/LTQy8ctvVTtq+Dg== X-IronPort-AV: E=McAfee;i="6700,10204,11234"; a="54732005" X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="54732005" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 14:47:06 -0700 X-CSE-ConnectionGUID: pt6qWDt6R6++P7lrQy3Vpg== X-CSE-MsgGUID: xGrB4lB7Td2EKVptxyYS/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="80809805" Received: from cataylo2-desk.jf.intel.com ([10.165.21.140]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2024 14:47:05 -0700 From: Clint Taylor To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: [PATCH v2 08/12] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register Date: Wed, 23 Oct 2024 14:46:57 -0700 Message-Id: <20241023214701.963830-9-clinton.a.taylor@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241023214701.963830-1-clinton.a.taylor@intel.com> References: <20241023214701.963830-1-clinton.a.taylor@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 +++++++++---- .../gpu/drm/i915/display/skl_universal_plane_regs.h | 1 + 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index a0a7ed01415a..60ca4f8c4a3c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1567,17 +1567,22 @@ skl_plane_async_flip(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - u32 plane_ctl = plane_state->ctl; + u32 plane_ctl = plane_state->ctl, plane_surf; plane_ctl |= skl_plane_ctl_crtc(crtc_state); + plane_surf = skl_plane_surf(plane_state, 0); - if (async_flip) - plane_ctl |= PLANE_CTL_ASYNC_FLIP; + if (async_flip) { + if (DISPLAY_VER(display) >= 30) + plane_surf |= PLANE_SURF_ASYNC_UPDATE; + else + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + } intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), plane_ctl); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), - skl_plane_surf(plane_state, 0)); + plane_surf); } static bool intel_format_is_p01x(u32 format) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 4ddcd7d46bbd..ff31a00d511e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -159,6 +159,7 @@ _PLANE_SURF_2_A, _PLANE_SURF_2_B) #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) +#define PLANE_SURF_ASYNC_UPDATE REG_BIT(0) #define _PLANE_KEYMAX_1_A 0x701a0 #define _PLANE_KEYMAX_2_A 0x702a0