diff mbox series

drm/xe/hdcp: Fix gsc structure check in fw check status

Message ID 20241025160834.8785-1-suraj.kandpal@intel.com (mailing list archive)
State New
Headers show
Series drm/xe/hdcp: Fix gsc structure check in fw check status | expand

Commit Message

Suraj Kandpal Oct. 25, 2024, 4:08 p.m. UTC
Fix the condition for gsc structure validity in
gsc_cs_status_check(). It needs to be an OR and not an AND
condition

Fixes: b4224f6bae38 ("drm/xe/hdcp: Check GSC structure validity")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Matt Roper Oct. 25, 2024, 4:12 p.m. UTC | #1
On Fri, Oct 25, 2024 at 09:38:35PM +0530, Suraj Kandpal wrote:
> Fix the condition for gsc structure validity in
> gsc_cs_status_check(). It needs to be an OR and not an AND
> condition
> 
> Fixes: b4224f6bae38 ("drm/xe/hdcp: Check GSC structure validity")
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> index 6d34b55d72bb..7c02323e9531 100644
> --- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> +++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
> @@ -44,7 +44,7 @@ bool intel_hdcp_gsc_check_status(struct intel_display *display)
>  	bool ret = true;
>  	unsigned int fw_ref;
>  
> -	if (!gsc && !xe_uc_fw_is_enabled(&gsc->fw)) {
> +	if (!gsc || !xe_uc_fw_is_enabled(&gsc->fw)) {
>  		drm_dbg_kms(&xe->drm,
>  			    "GSC Components not ready for HDCP2.x\n");
>  		return false;
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
index 6d34b55d72bb..7c02323e9531 100644
--- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
+++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
@@ -44,7 +44,7 @@  bool intel_hdcp_gsc_check_status(struct intel_display *display)
 	bool ret = true;
 	unsigned int fw_ref;
 
-	if (!gsc && !xe_uc_fw_is_enabled(&gsc->fw)) {
+	if (!gsc || !xe_uc_fw_is_enabled(&gsc->fw)) {
 		drm_dbg_kms(&xe->drm,
 			    "GSC Components not ready for HDCP2.x\n");
 		return false;