| Message ID | 20241029140037.164687-1-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] drm/i915/xe3lpd: Power request asserting/deasserting | expand |
On Tue, 29 Oct 2024, Mika Kahola <mika.kahola@intel.com> wrote: > There is a HW issue that arises when there are race conditions > between TCSS entering/exiting TC7 or TC10 states while the > driver is asserting/deasserting TCSS power request. As a > workaround, Display driver will implement a mailbox sequence > to ensure that the TCSS is in TC0 when TCSS power request is > asserted/deasserted. > > The sequence is the following > > 1. Read mailbox command status and wait until run/busy bit is > clear > 2. Write mailbox data value '1' for power request asserting > and '0' for power request deasserting > 3. Write mailbox command run/busy bit and command value with 0x1 > 4. Read mailbox command and wait until run/busy bit is clear > before continuing power request. > > v2: Rename WA function (Gustavo) > Limit WA only for PTL platform with a TODO note (Gustavo) > Add TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY for clarity when writing > register data (Gustavo) > Move register defs from i915_reg.h to intel_cx0_phy_regs.h (Gustavo) > v3: use "struct intel_display" instead of "struct drm_i915_private" (Jani) > Move defs above C10 definitions in the > intel_cx0_phy_regs.h file (Gustavo) > Move drm_WARN_ON() inside WA function (Gustavo) > Rename workaround function as wa_14020908590() (Gustvo) > Use boolean enable instead of if-else structure (Gustavo) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 ++++ > drivers/gpu/drm/i915/display/intel_tc.c | 39 +++++++++++++++++++ > 2 files changed, 47 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index ab3ae110b68f..e04cf2e7c054 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -200,6 +200,14 @@ > #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) > #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) > > +#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) > +#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) > +#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) > +#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) (TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | \ > + REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val)) > + > +#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) > + > /* C10 Vendor Registers */ > #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) > #define C10_PLL0_FRACEN REG_BIT8(4) > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index 6f2ee7dbc43b..51e8f7b1b812 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -1013,6 +1013,38 @@ xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled) > return true; > } > > +static void wa_14020908590(struct intel_display *display, > + bool enable) > +{ > + bool error = false; > + > + /* check if mailbox is running busy */ > + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, > + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { > + drm_dbg_kms(display->drm, > + "Timeout waiting for TCSS mailbox run/busy bit to clear\n"); Just do drm_WARN() with the message here. > + error = true; > + goto out; > + } > + > + intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable); > + intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD, > + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | > + TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1)); > + > + /* wait to clear mailbox running busy bit before continuing */ > + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, > + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { > + drm_dbg_kms(display->drm, > + "Timeout after writing data to mailbox. Mailbox run/busy bit did not clear\n"); Ditto. > + error = true; > + goto out; > + } > + > +out: > + drm_WARN_ON(display->drm, error); This stringifies the literal "error", and nothing of value is printed to dmesg. > +} > + > static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable) > { > struct drm_i915_private *i915 = tc_to_i915(tc); > @@ -1022,6 +1054,13 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena > > assert_tc_cold_blocked(tc); > > + /* > + * Gfx driver WA 14020908590 for PTL tcss_rxdetect_clkswb_req/ack > + * handshake violation when pwwreq= 0->1 during TC7/10 entry > + */ > + if (DISPLAY_VER(i915) == 30) > + wa_14020908590(&i915->display, enable); Please don't add inline &i915->display, because all of them need to be changed sooner rather than later. Add a struct intel_display *display local variable, and pass that around. BR, Jani. > + > val = intel_de_read(i915, reg); > if (enable) > val |= XELPDP_TCSS_POWER_REQUEST;
On Tue, Oct 29, 2024 at 04:00:37PM +0200, Mika Kahola wrote:
...
> Use boolean enable instead of if-else structure (Gustavo)
Hmm... Not sure if I'm reading it correctly, maybe need to revisit v2.
Raag
On Tue, Oct 29, 2024 at 04:41:29PM +0200, Jani Nikula wrote: > On Tue, 29 Oct 2024, Mika Kahola <mika.kahola@intel.com> wrote: ... > > +static void wa_14020908590(struct intel_display *display, > > + bool enable) > > +{ > > + bool error = false; > > + > > + /* check if mailbox is running busy */ > > + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, > > + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { > > + drm_dbg_kms(display->drm, > > + "Timeout waiting for TCSS mailbox run/busy bit to clear\n"); > > Just do drm_WARN() with the message here. Rather, ret = intel_de_wait_for_clear(); if (drm_WARN(drm, ret, ...)) return; Cleaner? Raag
Quoting Raag Jadav (2024-10-29 13:56:33-03:00) >On Tue, Oct 29, 2024 at 04:00:37PM +0200, Mika Kahola wrote: > >... > >> Use boolean enable instead of if-else structure (Gustavo) > >Hmm... Not sure if I'm reading it correctly, maybe need to revisit v2. Yeah, this was Raag's suggestion. -- Gustavo Sousa > >Raag
> -----Original Message----- > From: Jadav, Raag <raag.jadav@intel.com> > Sent: Tuesday, 29 October 2024 19.03 > To: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; > Sousa, Gustavo <gustavo.sousa@intel.com> > Subject: Re: [PATCH v3] drm/i915/xe3lpd: Power request asserting/deasserting > > On Tue, Oct 29, 2024 at 04:41:29PM +0200, Jani Nikula wrote: > > On Tue, 29 Oct 2024, Mika Kahola <mika.kahola@intel.com> wrote: > > ... > > > > +static void wa_14020908590(struct intel_display *display, > > > + bool enable) > > > +{ > > > + bool error = false; > > > + > > > + /* check if mailbox is running busy */ > > > + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, > > > + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, > 10)) { > > > + drm_dbg_kms(display->drm, > > > + "Timeout waiting for TCSS mailbox run/busy bit to > clear\n"); > > > > Just do drm_WARN() with the message here. > > Rather, > > ret = intel_de_wait_for_clear(); > if (drm_WARN(drm, ret, ...)) > return; > > Cleaner? Maybe we could drop the drm_WARN_ON() completely? This is something that we are not really using elsewhere in the driver. Simply drm_dbg_kms() on timeouts has so far been enough. What do you think? > > Raag
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index ab3ae110b68f..e04cf2e7c054 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -200,6 +200,14 @@ #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) +#define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) +#define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) +#define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) +#define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) (TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | \ + REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val)) + +#define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) + /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) #define C10_PLL0_FRACEN REG_BIT8(4) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 6f2ee7dbc43b..51e8f7b1b812 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -1013,6 +1013,38 @@ xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled) return true; } +static void wa_14020908590(struct intel_display *display, + bool enable) +{ + bool error = false; + + /* check if mailbox is running busy */ + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { + drm_dbg_kms(display->drm, + "Timeout waiting for TCSS mailbox run/busy bit to clear\n"); + error = true; + goto out; + } + + intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable); + intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY | + TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1)); + + /* wait to clear mailbox running busy bit before continuing */ + if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD, + TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) { + drm_dbg_kms(display->drm, + "Timeout after writing data to mailbox. Mailbox run/busy bit did not clear\n"); + error = true; + goto out; + } + +out: + drm_WARN_ON(display->drm, error); +} + static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable) { struct drm_i915_private *i915 = tc_to_i915(tc); @@ -1022,6 +1054,13 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena assert_tc_cold_blocked(tc); + /* + * Gfx driver WA 14020908590 for PTL tcss_rxdetect_clkswb_req/ack + * handshake violation when pwwreq= 0->1 during TC7/10 entry + */ + if (DISPLAY_VER(i915) == 30) + wa_14020908590(&i915->display, enable); + val = intel_de_read(i915, reg); if (enable) val |= XELPDP_TCSS_POWER_REQUEST;
There is a HW issue that arises when there are race conditions between TCSS entering/exiting TC7 or TC10 states while the driver is asserting/deasserting TCSS power request. As a workaround, Display driver will implement a mailbox sequence to ensure that the TCSS is in TC0 when TCSS power request is asserted/deasserted. The sequence is the following 1. Read mailbox command status and wait until run/busy bit is clear 2. Write mailbox data value '1' for power request asserting and '0' for power request deasserting 3. Write mailbox command run/busy bit and command value with 0x1 4. Read mailbox command and wait until run/busy bit is clear before continuing power request. v2: Rename WA function (Gustavo) Limit WA only for PTL platform with a TODO note (Gustavo) Add TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY for clarity when writing register data (Gustavo) Move register defs from i915_reg.h to intel_cx0_phy_regs.h (Gustavo) v3: use "struct intel_display" instead of "struct drm_i915_private" (Jani) Move defs above C10 definitions in the intel_cx0_phy_regs.h file (Gustavo) Move drm_WARN_ON() inside WA function (Gustavo) Rename workaround function as wa_14020908590() (Gustvo) Use boolean enable instead of if-else structure (Gustavo) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 ++++ drivers/gpu/drm/i915/display/intel_tc.c | 39 +++++++++++++++++++ 2 files changed, 47 insertions(+)