From patchwork Fri Nov 1 06:27:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jouni_H=C3=B6gander?= X-Patchwork-Id: 13858774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91364E674A8 for ; Fri, 1 Nov 2024 06:27:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10CB610E951; Fri, 1 Nov 2024 06:27:52 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ClEiITaV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5017C10E1BB; Fri, 1 Nov 2024 06:27:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730442471; x=1761978471; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YXfTYHnqQ9LtDKtQ45O1NK3Dk3pGZXye475kLy7b5io=; b=ClEiITaVh2YRHbTmS4rupvAzQMU7cXPb7AYblwmnvOasvZtp0JXvNXA/ pHujDZBc8gBgRkpWWXCIWQIIZtQwM0cBaJJCpk8huaRH3PMjp3/mp2pJi I0fw3pAy51f01aJg1txQbod+AjrOs98QYD7mVj6jcUar9gE/BUt7XBqMe +LFx2z1XmYF0PVc/co+LTMI5oDeAjuP2D31JyYVf9bp4sQwhsFsiWZRoa 8w5aGZFaZJW+OTktO2+9+eCkT1P2UTX7iAJ8rQwWvkGUt/hiWFXr3xV3Y xRZUv0NGkZDKaKURxq8EZ0ljjV9P9k6qg/n6wy1hD/mcj/OLKlSAWQOZ/ w==; X-CSE-ConnectionGUID: x9iWiHJ3TsCZiJz8fA2P+w== X-CSE-MsgGUID: j06TZYFwRsG9TUmER9njIw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="41306058" X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="41306058" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 23:27:50 -0700 X-CSE-ConnectionGUID: mg9CXH6UTfW6FF94AKAU0g== X-CSE-MsgGUID: I15hErYTR3eUDr0d5RJ4hQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,199,1725346800"; d="scan'208";a="87648567" Received: from ksztyber-mobl2.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.3]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 23:27:49 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH v2 1/7] drm/i915/psr: Add TRANS_PUSH register bit definition for PSR Date: Fri, 1 Nov 2024 08:27:22 +0200 Message-Id: <20241101062728.3865980-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241101062728.3865980-1-jouni.hogander@intel.com> References: <20241101062728.3865980-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add TRANS_PUSH register bit LNL_TRANS_PUSH_PSR_PR_EN definition for PSR usage. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..50540eac61a3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -100,6 +100,7 @@ #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) #define TRANS_PUSH_EN REG_BIT(31) #define TRANS_PUSH_SEND REG_BIT(30) +#define LNL_TRANS_PUSH_PSR_PR_EN REG_BIT(16) #define _TRANS_VRR_VSYNC_A 0x60078 #define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)