diff mbox series

[14/23] drm/i915/display: Handle transcoder timings for joiner

Message ID 20241111091221.2992818-15-ankit.k.nautiyal@intel.com (mailing list archive)
State New
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Ankit Nautiyal Nov. 11, 2024, 9:12 a.m. UTC 
Make sure the timing changes happen in the correct spot in the sequence
for both primary and secondary pipes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4b39692f57f6..6d7f54804542 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1783,7 +1783,6 @@  static void hsw_crtc_enable(struct intel_atomic_state *state,
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 	struct intel_crtc *pipe_crtc;
 	int i;
 
@@ -1819,8 +1818,14 @@  static void hsw_crtc_enable(struct intel_atomic_state *state,
 			bdw_set_pipe_misc(NULL, pipe_crtc_state);
 	}
 
-	if (!transcoder_is_dsi(cpu_transcoder))
-		hsw_configure_cpu_transcoder(new_crtc_state);
+	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
+		const struct intel_crtc_state *pipe_crtc_state =
+			intel_atomic_get_new_crtc_state(state, pipe_crtc);
+		enum transcoder cpu_transcoder = pipe_crtc_state->cpu_transcoder;
+
+		if (!transcoder_is_dsi(cpu_transcoder))
+			hsw_configure_cpu_transcoder(pipe_crtc_state);
+	}
 
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
 		const struct intel_crtc_state *pipe_crtc_state =